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Keynotes

Walid Najjar, University of California Riverside

Performance, Productivity and Programmability:

The Emergence of FPGA Code Accelerators

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Steve Trimberger, Xilinx Fellow

Programmable Logic and Moore's Two Laws

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Mike Hutton, Altera Corporation

Technology Issues Facing the World's Largest Integrated Circuits

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Performance, Productivity and Programmability:

The Emergence of FPGA Code Accelerators

A large number of studies have repeatedly demonstrated the ability of FPGA accelerators to achieve one to four orders of magnitude speed-ups over software execution. This is due to (1) the elimination of the overhead endemic in the stored program model (load, store and control instructions), (2) the deployment of large scale operation, loop and thread parallelism, and (3) customized pipelined data-paths supporting data reuse and variable bit width data. However, their poor programmability continue to be the main obstacle to their wider adoption. ROCCC (Riverside Optimizing Compiler for Configurable Computing) is an innovative C to VHDL compilation framework specifically focused on FPGA-based code acceleration. Its focus is on extensive and unique loop analysis techniques to implement advanced compile time transformations and optimizations aimed at generating an efficient circuit from a loop nest. ROCCC 2.0 goes a step further in bridging the gap between the temporal programming model inherent in C and the spatial programming model specific to hardware by supporting a bottom-up modular design approach and the reuse of existing codes while maintaining full compatibility with C. Existing C, VHDL and netlist modules can be imported into C source codes. ROCCC 2.0 is a free and open source tool that has been ported to a variety of platforms including the Convey Computers HC-1 and FPGA boards from Pico Computing. Applications developed with ROCCC, including image processing, computer vision, bioinformatics and data mining, have been shown to achieve two to four orders of magnitude speed-up over CPUs.
 

Programmable Logic and Moore's Two Laws

The success of the Programmable Logic has been dependent on the rapid pace of Moore's Law, which has made transistors cheap enough and fast enough that the overhead for programmability is acceptable. But while the cost of an individual transistor continues to fall, Moore's Second Law stated that the cost of setting up the manufacturing facility continues to rise. High initial costs make custom silicon too expensive for all but the highest-volume devices. This seems to indicate a bright future for programmable logic. However, the path is not all that clear. Power and concurrent design issues threaten the pace of Moore's Law. Will these new issues drive more designs toward programmable logic solutions, or will they drive them away? This presentation describes these issues in a historical context and explains how programmable logic vendors can succeed with the new Moore's Law of the 21st Century.

Technology Issues Facing the World's Largest Integrated Circuits

FPGAs are amongst the world's largest and most complex integrated circuits, and they continue to be very early adopters of the latest process technology. This talk will describe some of the driving applications and technology trends pushing FPGAs to 28 nm and smaller process nodes. We will also highlight how FPGA architecture is evolving, as exemplified by Altera's Stratix V FPGAs. Power management and silicon efficiency issues are pushing FPGAs to become somewhat more application-targeted, and to incorporate larger amounts of hard logic that makes them more complete systems-on-a-chip. In addition, the very high I/O bandwidth requirements of next-generation systems are driving innovation in both high-speed memory interface design and high-speed serial transceiver design.

Stratix V supports partial reconfiguration to increase silicon efficiency by swapping in different functionality over time. We will describe both the hardware that enables partial reconfiguration, and the software tools that will enable efficient design without becoming entangled in low-level physical details. Finally, we will discuss both software challenges and promising research efforts to create CAD tools that will help designers productively create the very large systems enabled by modern FPGAs.