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As other editions, SPL2011 will feature a Tutorial program from April 11 to 12 (i.e., the two days previous the conference) and on Friday 15 afternoon. Tutorials will be OPEN to ALL conference attendees FREE of charge. Registration to tutorials will be available through EDAS from February 28 to March 10. For any question, please contact:

Tutorial Registration:


Monday 11

Tuesday 12

9:00 - 13:00

Fast Prototyping using Synopsys Tools

Victor Grimblatt, R&D Director
Synopsys Chile

Tutorial Slides

13:00 - 14:00 Break
14:00 - 18:00

Embedded Systems
in Altera FPGAs

Designing with Altera DSP Builder

Fabio Petrassem de Sousa, Director
DHW Engenharia e Representacao Ltda

Friday 15

15:00 - 17:00

The software migration of hardware design tools

Carlos Valderrama, Professor Department Director, University of Mons, Polytechnic Faculty, Electronics and Microelectonics Department SEMi,
Mons, Belgium.


Fast Prototyping using Synopsys Tools

Time to market has become a critical issue when developing electronic systems. Not only we need to develop the hardware of our system very fast but we also need to have first silicon success and allow software designers to start developing the product as early as possible in the product design cycle. New tools have appeared in the market that provide us the capability to reduce the time to market while improving the probability to get first silicon success and providing software engineers with early platforms to develop the product software. The tutorial will cover the different existing challenges when developing electronic systems and will introduce new tools such as virtual platform and fast prototyping platforms that allow designers to cope with those challenges.

Tutorial Slides

Victor Grimblatt has a Microelectronic Engineer degree from Institut Nationale Polytechnique de Grenoble, France and an Electronics Engineer degree from Universidad Tecnica Federico Santa Maria (Chile). He has more than 25 years experience in Electronics System Design and EDA (Electronic Design Automation) working at different multinational companies such as Honeywell Bull, VLSI Technology Inc., Compass Design Automation, and Motorola. Currently, he manages a Synopsys R&D Center in Santiago Chile and is professor at Universidad de Chile and Universidad de los Andes.


Embedded Systems with Altera FPGAs

This course will teach you how to design in a soft core embedded processor with an Altera FPGA. This course is focused on the hands-on development of Nios II hardware and software using the Nios® II Development Kit. You will learn how to integrate a Nios II 32-bit microprocessor and test it in an Altera FPGA. You will learn how to configure and compile designs using the Quartus® II software v. 10.1 and SOPC Builder tool as well as how to develop and run embedded software for the Nios II processor in the Nios II Software Build Tools for Eclipse. After taking this course you should feel confident tackling your next SOPC design.
- Background in digital logic design
- Working knowledge of the Quartus II design software
- Some knowledge of programming in C for embedded systems

Designing with Altera DSP Builder

Learn the FPGA design flow for implementing DSP designs. You will use DSP Builder which is an interface between the Quartus® II software v. 10.1 & Mathworks` Matlab Simulink tools. You will analyze, design, implement, & verify DSP systems using the DSP Builder blockset in Matlab & Simulink.
- Background in digital logic design
- Familiarity with DSP fundamentals and design
- Familiarity with Altera® FPGA architecture is helpful, but not necessary
- Familiarity with Mathworks Matlab and Simulink are helpful, but not necessary

Speaker profile:

Fábio Petrassem de Sousa graduated in 1995 in Electrical Engineering at UFSC (Brazil), Fabio has specialized in Digital Logic designs (mainly based in programmable logic technology) and worked in several technology companies in Brazil for 6 years (1995-2000). After working during the year 2000 in Sao Paulo as a Field Applications Engineer for the Altera distributor in Brazil, he was invited to join the Altera Corporation development team, at the Altera European Technology Centre in the UK, as a Senior Hardware Design Engineer. For 5 years he was responsible for designing hardware in all levels, from silicon to application. While working at Altera Fabio was also a Project Coordinator and Team Leader, publishing papers and creating patents for the company. In 2006Fabio returned to Brazil to open DHW Engineering to provide consultancy in hardware and software projects, creating a large portfolio of applications and customers in Brazil and abroad. DHW has also formalized a partnership with Altera Corporation on both Design Services and Training, as part of the ACAP and ATPP programs. In 2009 DHW was chosen to be the Altera Representative in South America, and Fabio is currently the Director of the company.


FPGA AND ASIC CONVERGENCE: The software migration of hardware design tools

The growing demands on multimedia applications and high-speed high-quality telecommunication systems with real-time constrains oriented to portable, low power consumption, devices, have being driven technologies development, methodologies and design flows of embedded systems during the last years. Through the analysis of design methodologies and strategies facing multi-core, reconfigurability and power consumption challenges, this educational survey will follow that evolution approaching ASIC and FPGA architectures on the embedded systems arena.

Speaker profile:

Carlos Valderrama is the Director of the Electronics and Microelectronics Department of the University of Mons, in Belgium since 2003. He also holds a visiting faculty position at the Universities of Rio Grande do Norte (UFRN) and Pernambuco (UFPE), both in Brazil. He was also manager at CoWare (acquired by Synopsys in 2010), in Belgium, dedicated to EDA/ESL design tools. He was also responsible for the creation of the spinoff nSilition dedicated to analog/mixed signals solutions and IC design services. He received a PhD degree in electrical engineering from the Institut National Polytechnique de Grenoble (INPG), France, in 1998 and the MSc degree from the Federal University of Rio de Janeiro (UFRJ), Brazil, in 1993. He received the Best Paper Award at the 1994 ED&TC for his work on Hardware/Software co-simulation and in 2001 at the SBCCI 2002/IEEE Symposium on Integrated Circuits and System Design. He is today IEEE senior member.


Professor Valderrama’s research interests are power processing, consumption and management. He is active in the area of embedded applications, wireless smart sensors for logistics, and signal processing for biomedical and telecommunication applications, among others. His main research activities are methodologies and tools for the design of multi-core architectures and SoC platforms for embedded applications. He is currently member of several scientific committees of international conferences (DAC, FPL, RAW, IDT, ReConfig and Iberchip among others). His research activity is supported by several publications and books chapters, and tutorials.