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Organized by

Call for Papers

The Program Committee cordially invites you to participate and submit your contribution to SPL2012. If you prefer you can download the Call For Papers.

The conference topics are within the scope of field reconfigurable logic and its applications. A non exclusive list of themes is:

 

Design Methodology Low-Power Design High-speed Techniques Physical Design Dynamic Reconfiguration Interconnects and NoCs    EDA Tools Logic and Architectural Synthesis Modelling and Simulation Emulation CAD for reconfigurable architectures Reconfigurable hardware design languages System-level design methods Testing, verification and benchmarking Hardware/software co-design

Platform-based Design Embedded Processors Custom Computers Reconfigurable Multicore IP Cores Signal Processing Computer Arithmetics Digital Signal Processing Adaptive Signal Processing Image and Video Processing FPGA in Education Roadmap of programmable logic Teaching Reconfigurable systems Emerging Device technologies

Applications Communications Networks Artificial vision Cryptography Bioinformatics Application acceleration Rapid prototyping High performance computing Multimedia Reliable Embedded Applications Design verification and validation Reliability and fault tolerance FIT rates analysis High reliability processor cores Noise, radiation effects and EMC

Conference Papers

Authors are invited to submit original and unpublished contributions as 6-page papers. The page limit includes tables, figures and references. Papers must be written in English. As previous editions, accepted papers will published in the IEEE Xplore digital library.

 

Designer Forum Papers

Authors interested in contributing to the Designer Forum are invited to submit 4-page papers. This forum is held to give exposure to ongoing works, academic experiences, and industrial designs in order to get feedback from experienced researchers and industrial partners. Due to the regional scope of this forum, papers can be written also in Spanish and Portuguese. Accepted contributions will be included in a separate proceeding but not in the IEEE library.

 

Important Dates

SPL Submission Deadline: Oct/17 Extended Deadline: Oct/24
SPL Notification of Acceptance: Dec/12
Designer Forum Submission Deadline: Dec/23 Extended Deadline: Jan/09
Designer Forum Notification of Acceptance: Jan/23
SPL and Designer Forum Camera-Ready Deadline: Feb/13

 

Paper Templates

Word Template to prepare your papers [.doc]

LaTeX Template to prepare your papers [.zip]

LaTeX Bibliography Files [.zip]

 

Best Papers

Best papers from the SPL 2012 conference will be invited to submit an extended version for publication in the International Journal of Reconfigurable Computing (ISSN 1687-7195) and the Journal of Integrated Circuits and Systems (ISSN 1807-1953). 

Altera Best Paper Award: The Program Committee will select the best paper based on Altera FPGAs that was presented at SPL 2012. The author of this paper will be rewarded with a DE0 prototyping board gently donated by Altera Corporation and a diploma provided by the event organization.  

Xilinx Best Paper Award: This award is currently being negotiated with Xilinx Inc.  

 

For further details on paper submission guidelines and procedures visit the Paper Submission section.