SPL 2012 Keynotes
Keynote 1
March, 21st - Wednesday
09:00h - 10:30h
Partially Reconfigurable Systems: Past, Present and Future Perspective
Ney Laert Vilar Calazans and Fernando Gehm Moraes (PUC-RS, Brazil)
Keynote Summary: A partially reconfigurable (PR) system is a digital system where selected blocks can be structurally and/or functionally modified along the system lifetime. Of particular interest are systems where modifications may take place during system operation, the so-called dynamic PR (DPR) systems. Although reconfigurable devices as FPGAs are a close-to-ideal substrate to produce PR/DPR systems, the concept is older than FPGAs themselves and has been implemented in several technologies and flavors. This keynote approaches the history of PR/DPR systems, the principles behind the concept and its evolution until the current state of the art. Also, some perspectives into future development for the subject are advanced.
Short Bio: Received a PhD degree in Microelectronics in 1993, from the Université Catholique de Louvain (UCL), Belgium, and a Computer Science MSc and Electrical Engineering Bachelor degrees from the Federal University of Rio Grande do Sul (UFRGS), Brazil, in 1988 and 1985, respectively. Ney Calazans is currently a Professor at the Pontifical Catholic University of Rio Grande do Sul (PUCRS), where he has worked for the last 25 years. He founded the Hardware Design Support Group (GAPH) and is currently the co-head of this group, together with Prof. Fernando Gehm Moraes. The GAPH is well known in Brazil and abroad for its contributions in several domains, including: (1) the Hermes network on chip (NoC), the Atlas automatic NoC generation environment and around a dozen alternative NoC designs; (2) the HeMPS multiprocessor system on a chip (MPSoC) and the HeMPSGenerator automatic MPSoC generation and configuration environment; and other contributions, most available and open to the research community. The research interests of Prof. Calazans include intrachip communication networks, non-synchronous circuit design and implementation, fast prototyping of circuits and systems and computer-aided design techniques and tools for digital circuits. Prof. Calazans counts around 130 publications on his fields of interest, among journal articles, conference papers, books chapters and books. He is a member of the IEEE, of the Brazilian Computer Society, SBC, and of the Brazilian Society of Microelectronics, SBMICRO.
Keynote 2
March, 22nd - Thursday
09:00h - 10:30h
Programming Abstractions for FPGAs using OpenCL
Shawn Slockers (Altera – US), Computer & Storage Specialist
Keynote Summary: Programmable solutions have evolved over time to a point that multicore processors are mainstream - some processors may have hundreds of specialized processing cores. Programmers must write software with this parallel hardware in mind. The multitude of programmers targeting parallel cores, coupled with FPGA logic densities that are increasing at a frantic pace, make a compelling case for a higher level abstraction for FPGA coding, moving away from traditional RTL. OpenCL is an open language that offers a multicore programming model and abstracts away the underlying hardware, easing design entry targeting FPGAs.
Short Bio: Shawn Slockers has a Master of Electrical Engineering degree and a Bachelor of Science in Electrical Engineering degree, both from Rice University in Houston, TX. Shawn’s professional career has centered around electronics design, including high-speed board and FPGA design, focused on high-throughput FPGA-based systems transporting data between frontend I/O, high-throughput memory banks, and backend system processor interfaces. FPGAs in these systems have evolved from basic traffic management to powerful compute nodes in heterogeneous computing systems.
Keynote 3
March, 23rd - Friday
09:00h - 10:30h
Digital IC Design: Flow, Challenges, and Low Power
Victor Grimblatt (Synopsys R&D Center - Chile, Universidad de Chile, Universidad de los Andes)
Keynote Summary: New technologies, smaller transistors, low power requirements have changed the way people design chips. Some years ago the distinction between front-end and back-end of IC design was really clear and engineers were expert in one of the topics. Today there are physical considerations that should be taken in account during the RTL design phase to ensure the feasibility of the chip. The presentation will present how the design flow covers the new challenges and how it addresses the low power requirements. FinFET transistors will also be presented.
Short Bio: Victor Grimblatt has a Microelectronic Engineer degree from Institut Nationale Polytechnique de Grenoble, France and an Electronics Engineer degree from Universidad Tecnica Federico Santa Maria (Chile). He has more than 25 years experience in Electronics System Design and EDA (Electronic Design Automation) working at different multinational companies such as Honeywell Bull, VLSI Technology Inc., Compass Design Automation, and Motorola. Currently, he manages a Synopsys R&D Center in Santiago Chile and is professor at Universidad de Chile and Universidad de los Andes.