Technical Sponsorship

IEEE

CAS



Financial Support

Capes

CNPq

FAPERGS



Supported by

SBMICRO

SBC

EUROFORM

CAS-RS

Program at a Glance

Hour March/20th March/21st March/22nd March/23rd
08:00-09:00 Registration Registration Registration Registration
09:00-10:30 Tutorial 1 Keynote 1 Keynote 2 Keynote 3
10:30-11:00 Coffee-Break Coffee-Break Coffee-Break
11:00-12:30 SPL Oral Session 1 SPL Oral Session 3 SPL Oral Session 4
12:30-14:00 Lunch Lunch Lunch Lunch
14:00-15:30 Tutorial 2 DF Poster Session SPL Poster Session 1 SPL Poster Session 2
15:30-16:00 Coffee-Break Coffee-Break Coffee-Break
16:00-17:30 SPL Oral Session 2 Companies Exhibition SPL Oral Session 5
17:30-18:30 Registration Opening Ceremony   Closing Ceremony
19:30   Welcome Cocktail Friendship Dinner  

 

March, 20th - Tuesday

09:00 - Tutorial 1
     Title: Implementing Emdedded Systems in FPGAs using Qsys
     Fábio Petrassem de Souza (DHW Engineering)

12:30 - Lunch

14:00 - Tutorial 2
     Title: Digital TV – The challenges of a New Media
     Altamiro Amadeu Susin (UFRGS, Brazil)

March, 21st - Wednesday

09:00 - Keynote 1
     Title: Partially Reconfigurable Systems: Past, Present and Future Perspective
     Ney Laert Villar Calazans and Fernando Gehm Moraes (PUC-RS, Brazil)

10:30 - Coffee-Break

11:00 - SPL Oral Session 1
     SoC - MPSoC - NoC

     An Open-source Framework for Heterogeneous MPSoC Generation
     Eduardo Wächter, Carlo Lucas, Everton Carara and Fernando Moraes

     A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
     Sol Pedre, Tomas Krajnik, Elias Todorovich and Patricia Borensztejn

     HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping
     Guilherme Heck, Ricardo Guazzelli, Rafael Soares, Fernando Moraes and Ney Calazans

     Memory Bandwith Reduction in Video Coding Systems Through Context Adaptive Lossless Reference Frame Compression
     Dieison Silveira, Gustavo Sanchez, Mateus Grellert, Vinicius Possani and Luciano Agostini
 

12:30 - Lunch

14:00 - DF Poster Session

     Comparación del consumo de energía de diferentes arquitecturas para multiplicación de matrices en FPGA
     Rodrigo González, Gustavo Sutter

     Controlador de interrupciones para el protocolo Daisy Chain de Zilog
     Juan Manuel Torterolo, Sebastián Torterolo, Leonardo Etcheverry, Julio Pérez Acle

     Emulador de Motor DC em Hardware
     Lucas W. Schuch, Vagner S. Rosa

     FPGA Implementation of Synchronous Finite State Machines Partitioned with One-hot Enconding
     Duarte L. Oliveira, Lester A. Faria, Luiz S. Ferreira

     Low cost monitoring video system
     María Isabel Schiavon, Daniel Alberto Crepaldo, Raúl Lisandro Martín, Javier Ghorghor

     Mexbox: a platform for FPGA embedded computing
     Gerardo Rosas, Miguel Arias-Estrada

     Projeto e Desenvolvimento de um Microprocessador Compatível com a ISA do MSP430
     Alex Gonçalves Saraiva, Diógenes C. da Silva Júnior

     Quantum Algorithms Simulation on FPGAs
     Calebe Conceição, Ricardo Reis

     Reconfigurable Architecture Implementation for the 1-D Discrete Cosine Transform
     Bruno Hecktheuer, Ruhan Conceição, José Souza Júnior, Ricardo Jeske, Luciano Agostini, Julio C. Mattos

     SystemC Model of a Memory Controller for Digital TV Set-Top Box Multilevel Simulation
     A. C. Bonatto, A. B. Soares, A. A. Susin

     uLab Virtual Controls
     Miguel Risco-Castillo
     

15:30 - Coffee-Break

16:00 - SPL Oral Session 2
     Image and Video Processing

     Real Time QHDTV Motion Estimation Architecture Design for DMPDS Algorithm
     Gustavo Freitas Sanchez, Marcelo Porto, Sergio Bampi and Luciano Agostini

     Hardware-based computation of the roughness index for infrared imagers
     Rodolfo Redlich, Gonzalo Carvajal, Miguel Figueroa and Juan Pablo Moreno

     A High Performance and Low Memory Bandwidth Architecture for Motion Estimation Targeting High Definition Digital Videos
     Alba Sandyra Bezerra Lopes, Ivan Saraiva Silva and Luciano Volcan Agostini

     Memory Efficient FPGA Implementation of Motion and Disparity Estimation for the Multiview Video Coding
     Felipe Sampaio, Bruno Zatt, Sergio Bampi and Luciano Agostini
 

17:30 - Opening Ceremony

19:30 - Welcome Cocktail

March, 22nd - Thursday

09:00 - Keynote 2
     Title: Programming Abstractions for FPGAs using OpenCL
     Shawn Slockers (Altera – US), Computer & Storage Specialist

10:30 - Coffee-Break

11:00 - SPL Oral Session 3
     Digital Signal Processing

     A Fast Interpolative Wordlength Optimization Method for DSP Systems
     Enrique Sedano, Juan A. López and Carlos Carreras

     Low Cost and High Throughput Multiplierless Design of a 16 Point 1-D DCT of the New HEVC Video Coding Standard
     Ricardo Jeske, José Cláudio De Souza Jr., Gustavo Wrege, Ruhan Conceição, Mateus Da Silva, Júlio Mattos and Luciano Agostini

     An MPEG-4 AAC decoder FPGA implementation for the Brazilian Digital Television
     Adriano Renner and Altamiro Susin

     Very High Throughput FPGA Design for Vertical Rotational Transform of HEVC Emergent Video Coding Standard
     Henrique Vianna, Virginia Andersson, Gustavo Sanchez and Luciano Agostini
 

12:30 - Lunch

14:00 - SPL Poster Session 1
     System-on-a-Chip

     The Impact of Operating System Adoption in an Embedded Project: a Case Study
     Ricardo Jasinski, Maiko Moroz and Volnei Pedroni

     Memory-mapped I/O over Dual Port BRAM on FPGA
     Rodrigo Melo, David Caruso and Salvador Tropea

     Design of an 8192-bit RSA Cryptoprocessor based on Systolic Architecture
     Claudia Patricia Renteria Mejia, Vladimir Trujillo and Jaime Velasco-Medina

     A novel Application of FPGA-Based Partial Dynamic Reconfiguration System with CBSC
     Chenguang Guo

     HW/SW FPGA Design for Active Control of Flexible Structures
     Leonardo Bandeira Soares, Marco Terres, Sebastião Gomes, Vitor Gervini and Vagner Rosa

     Implementation of a Fully Pipelined BCD Multiplier in FPGA
     Carlos Minchola

     Secure ConīŦguration Schemes for FPGA-based Systems with Simple Key Management
     Abdelghani Errandani, Abderrahim Doumar and Eric Châtelet

     Clock Gating and Clock Enable for FPGA Power Reduction
     Juan Oliver, Juan Curto, Diego Bouvier, Manuela Ramos and Eduardo Boemo

     Revisiting Atari 2600 on an FPGA
     Guilherme Flach, Calebe Conceição, Marcelo Johann and Ricardo Reis

     Adapting a Low Complexity Datapath to MIPS-1
     Leonardo Casillo and Ivan Saraiva

     Integration of IPs into the M8051 Microcontroller
     Thiago Mussolini, Tales Pimenta, Robson Moreno, Paulo Crepaldi and Leonardo Zoccal
 

15:30 - Coffee-Break

16:00 - Companies Exhibition
     Agilent Technologies

16:25 - Companies Exhibition
     Tectronix

16:50 - Companies Exhibition
     Anacom - XILINX

17:15 - Companies Exhibition
     DHW - Altera

19:30 - Friendship Dinner

March, 23rd - Friday

09:00 - Keynote 3

     Title: Digital IC Design: Flow, Challenges, and Low Power
     Victor Grimblatt (Synopsys R&D Center - Chile, Universidad de Chile, Universidad de los Andes)

10:30 - Coffee-Break

11:00 - SPL Oral Session 4
     Advanced Applications

     FPGA IMPLEMENTATION OF ROBUST ASYNCHRONOUS WRAPPERS FOR GLOBALLY–ASYNCHRONOUS LOCALLY–SYNCHRONOUS SYSTEMS (GALS)
     Duarte L. Oliveira L. Oliveira, Lester De Abreu Faria and Eduardo Lussari

     WL-Emap: Wirelength prediction based technology mapping for FPGAs
     Rodrigo Savage, Senthilkumar Rajavel and Ali Akoglu

     Historic Behavior of the Electronic Technology: The Wave of Makimoto and Moore's Law in the Transistor's Age
     Pablo A. Salvadeo, Angel C. Veca and Rafael Castro Lopez

     Real-Time Scheduling Coprocessor for NIOS II Processor.
     Martín Varela, Ricardo Cayssials, Edgardo Ferro and Eduardo Boemo.
 

12:30 - Lunch

14:00 - SPL Poster Session 2
     Digital Signal Processing and Education

     FPGA Design of H.264/AVC Intra-Frame Prediction Architecture for High Resolution Video Encoding
     Cláudio Diniz, Altamiro Susin and Sergio Bampi

     FPGA Based Hardware Architecture for Motion Vector Predicton in H.264/AVC Encoders Targeting HD1080p Resolution
     Daniel Palomino, Felipe Sampaio, Sergio Bampi, Altamiro Susin and Luciano Agostini

     Towards a Video Processing Architecture for SBTVD
     Marcelo Negreiros, Altamiro Susin, Alexsandro Bonatto, Andre Borin and Henrique Klein

     A High Throughput Configurable FFT Processor for WLAN and WiMax Protocols
     Renan Oliveira Netto and Jose Luis Guntzel

     Optimized 16x16 Discrete Cosine Transform Architecture for Homogeneity-Based H.264/AVC Intra Mode Decision
     Renato Souza, Roger Porto, Leomar Da Rosa Jr. and Luciano Agostini

     Background Subtraction Algorithm for Moving Object Detection in FPGA
     Camilo Sánchez-Ferreira, Jones Yudi Mori and Carlos Humberto Llanos

     Image Convolution Processing: a GPU versus FPGA Comparison
     Lucas Russo, Emerson Pedrino, Edilson Kato and Valentin Roda

     An Efficient Packing Algorithm Based on Constraint Satisfaction Problem Technique
     Meng Yang and Jiarong Tong

     FPGA Implementation of Hardware countermeasures
     Raúl Jiménez-Naharro, Guillermo Feria-Revilla, Manuel Sánchez-Raya, Juan-Antonio Gomez-Galan and Fernando Gómez-Bravo

     Applying in education an FPGA-based methodology to emulate ASIC soft cores and test ICs
     Cezar Rodolfo Wedig Reinbrecht, Julio Leao Da Silva Jr and Eric Ericson Fabris

     A Basic Processor for Teaching Digital Circuits and Systems Design with FPGA
     Maicon Pereira, Paulo Vieira, André Raabe and Cesar Zeferino

15:30 - Coffee-Break

16:00 - SPL Oral Session 5
     Arithmetic Circuits

     GENERIC CONSTRUCTION OF MONITORS FOR FLOATING POINT UNIT DESIGNS
     Oscar Goñi, Oswaldo Cadenas and Elías Todorovich

     FPGA implementation of large-scale Matrix Inversion using single, double and custom floating-point precision
     Janier Arias-Garcia, Carlos Humberto Llanos, Mauricio Ayala-Rincon and Ricardo Jacobi

     FPGA Implementation of the Parity Check Node for Min-Sum LDPC Decoders
     Fernando Gutierrez, Graciela Corral-Briones and Damián Morero

     B-Spline Generation in FPGA
     Luiz Marcelo Chiesse Da Silva and Maria Stela Veludo De Paiva
 

18:30 - Closing Ceremony