Program at a Glance
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Tuesday, November 4 (Ciudad Universitaria) |
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9:00–12:30 |
Tutorial 1 Power-Temperature Basics on FPGA Eduardo Boemo (Universidad Autónoma de Madrid, Spain) Facultad de Ciencias Exactas y Naturales (FCEyN), UBA Ciudad Universitaria – Pabellón 1, Room 8 Summary: Review of ICs design fundamental for enginners interested on FPGA technology. Special emphasis on speed, power and thermal optimization. |
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15:30-18:00 |
Tutorial 2 The Art of Designing and Implementing Finite State Machines in Hardware Volnei A. Pedroni (Federal Technological University of Parana State, Brazil) Facultad de Ciencias Exactas y Naturales (FCEyN), UBA Ciudad Universitaria – Pabellón 1, Room 5 Summary: Very
few topics affect a larger audience of digital circuit designers and
instructors than the subject of correctly designing and implementing finite
state machines (FSMs) in hardware (as opposed to software). Such need is
crucial to the development of digital systems, particularly as their
complexity grows, and is aggravated by the fact that still only trivial
machines can be satisfactorily modeled by current electronic design
automation (EDA) tools.This tutorial is based on a recent publication by MIT
Press [1], which is the first work to specifically and extensively
investigate and describe the art of completely designing and implementing
FSMs in hardware.The first point discussed is what really differentiates one
FSM from another as far as hardware is concerned. It is shown that any FSM
falls in one of just three categories (proposed in a new classification),
called regular, timed, and recursive finite state machines. This led to the
development of three systematic design procedures, allowing any FSM to be
easily and optimally implemented in hardware. Other fundamental hardware
aspects are treated subsequently, including state encoding styles, input
signals conditioning, multiple clock domains and the use of synchronizers,
capture of initial values, the importance of reset, and the construction of
safe state machines. |
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Wednesday, November 5 (Palacio San Martín) |
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8:30-9:30 |
Registration |
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9:30-10:00 |
Opening |
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10:00-11:30 Keynote 1 |
Synopsys: “Fabless and IP: The opportunity for Latin America” Victor Grimblatt Summary: Since the invention of the transistor in 1947 and the integrated circuit in 1959 the semiconductor business has went through an interesting history starting at companies dedicated to the design and fabrication of their own chips, going through the ASIC business pioneered by VLSI Technology and LSI Logic, and ending at the fabless and IP business. Market needs, semiconductor technology, and EDA have been the drivers of this business changes and the role of electronics in today’s world. This talk will present the semiconductor business and related business since its start to current days, from an historical, technical, and economical point of view. It will focus on the fabless and IP business which are the real opportunities for Latin America. |
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11:30-12:30 |
Break & Poster Session 1 Efficient Hardware Design of N-point 1D-DCT for HEVC Jose Daniel BolaÑos Jojoa and Jaime Velasco Medina. FPGA-based Pipelined Cartesian-Polar Converter for Real-Time Video Processing Sergio Geninatti, Gerardo Gennai, Gustavo Minnucci and Eduardo Boemo. Hardware / Software Co-design for Acceleration of Image Processing using FPGA Miguel Ángel Carrazco Díaz, Susana Ortega Cisneros, Adrian Pedroza de La Cruz, Hector Cabrera Villaseñor, Juan José Raygoza Panduro and Jorge Rivera Domínguez. Image Processing systems in FPGA: Components-Connectors Methodology Miguel Angel García and Patricia Borensztejn. |
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13:30-15:30 |
Session 1: SoCP and IP Cores Wavelet Hardware Processing Unit for Transient Signal Detection Juan Marcos Macchi Konrad, Lorenzo De Pasquale, Miguel Banchieri, Ricardo Cayssials and Edgardo Ferro. An advanced NoC with Debug Services on FPGA Elías Todorovich, Matias Leonetti and Ray Brinks. Estimation of a FPGA binary32 floating point cube root Carlos Minchola Guardia. The Hamiltonian-based Odd-Even Routing Method for 3D Networks-on-Chip Poona Bahrebar and Dirk Stroobandt. |
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15:30-16:00 |
Break |
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16:00-18:00 |
Session 2: Digital Signal Processing Proposal for Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA Alisson de Souza and Marcelo Fernandes An image descriptors extraction hardware-architecture inspired on human retina Emmanuel Bello and Pablo A. Salvadeo. Hardware-accelerated spike train generation for neuromorphic image and video processing Taras Iakymchuk and Alfredo Rosado-Muñoz. FPGA structures for image comparison: Embedded vs distributed memory Sergio Geninatti, Gerardo Gennai, Santiago Roatta and Eduardo Boemo. |
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Tuesday, November 6 (Palacio San Martín) |
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8:30-9:00 |
Registration |
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9:00-10:30 Keynote 2 |
Altera: “Configuration of complex FPGA devices” Alfredo de la Cruz Summary: With new generations of FPGAs becoming extremely complex devices incorporating multi-core CPUs, a myriad of peripheral hardened-IPs and mind-boggling amounts of programmable logic; the configuration of such devices is becoming a true challenge for the overall success of the programmable-technology. FPGA configuration is faced against more-often-than-not conflicting demands as increased security, lower initialization time as well as smaller configuration bitstream sizes. All these requirements are also present during partial reconfiguration, which is a technology rapidly gaining acceptance among different applications environments, adding specific demands associated with the dynamics of the changes to the FPGA-device programming. During this keynote presentation, the author explores the multiple challenges facing the configuration of complex FPGA devices associated with CVP (Configuration Via PCIe), security, bitstream compression and SEU detection. He discusses the relation between CVP and early transceiver calibration within most recent Arria devices. In particular detail he focuses on the deeply cross-encountered requirements associated with partial reconfiguration, both in hardware as well in the CAD software tools, and examine them under the light of the approaches taken by some of the major FPGAs manufacturers, specifically Altera. He also surveys some of the existing solutions from these manufacturers to reduce the bitstream storage demands, associated with either full or partial reconfiguration, and project some possible future directions in these areas for the forthcoming years. |
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10:30-11:00 |
Break |
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11:00-13:00 |
Session 3: Computer Arithmetic and Cryptography Components for Coverage-Driven Verification of Floating-Point Unit Designs Oscar Goñi and Elias Todorovich Hardware Design of an NTT Polynomial Multiplier Claudia Patricia Renteria Mejia and Jaime Velasco Medina. PUF's Performance Evaluation Among Different Xilinx FPGAs Families Brisbane Ovilla-Martinez and Arturo Diaz-Perez. Design and Implementation of Decimal Fixed-Point Square Root in LUT-6 FPGAs Martín Vázquez and Marcelo Tosini. |
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14:00-15:30 Keynote 3 |
Xilinx: “Unlocking FPGAs Using High-Level Synthesis Compiler Technologies” Fernando Martinez Vallina FPGA devices have long been the standard for massively parallel computing fabrics with a low power footprint. Unfortunately, the complexity associated with an FPGA design has limited the rate of adoption by software application programmers. Recent advances in compiler and FPGA fabric capabilities are reversing this trend and there is a growing adoption of FPGAs for algorithmic workloads such as data analytics, feature detection in images, adaptive beam forming, etc. One of the pillars of this shift is the Vivado HLS compiler, which enables the compilation of algorithms captured in C and C++into efficient FPGA implementations. This talk focuses on how the HLS compiler creates algorithm specific compute architectures and removes the constraints designers face when dealing with fixed parallel architectures such as multi-core CPUs/GPUs. |
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15:30-16:00 |
Break |
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16:00-18:00 |
Session 4: Design Methodology Validation of an On-Chip Watchdog for Embedded Systems Exposed to Radiation and Conducted EMI Fabian Vargas, Christofer Oliveira, Juliano Benfica, Leticia Bolzani Poehls, Jose Lipovetzky, Ariel Lutenberg, Edmundo Gatti and Fernando Hernandez. Burst-Mode Asynchronous Controller Implementation on FPGA Using Relative Timing Jotham Vaddaboina Manoranjan and Kenneth S. Stevens. Power Estimations vs. Power Measurements in Spartan Devices Juan P. Oliver, Julio Perez Acle and Eduardo Boemo. Synthesis of Locally-Clocked Asynchronous Systems with Bundled-Data Implementation on FPGAs Kledermon Garcia, Duarte Oliveira, Tiago Curtinhas and Roberto D'Amore. |
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20:00- |
Conference Dinner |
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Friday, November 7 (Palacio San Martín) |
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8:30-9:00 |
Registration |
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9:00-11:30 |
Session 5: Applications |
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11:30-12:30 |
Break & Poster Session 2 Un Constructor Virtual y Simulador Lógico para el Descubrimiento y Diseño de Circuitos Digitales con Enfoque en Proyectos de Ingeniería Arturo Miguel-De-Priego. HTTP Secure Server in an Embedded System Oscar Alvarado-Nava, Eduardo Rodriguez-Martinez and Alejandro Cadena Cervantes. Improving fault tolerance in embedded applications with RobustO library Eduardo Alejandro Sanchez and Daniel Gutson. Development of a narrowband multichannel active noise control system for enclosures Leopoldo Budde and Roberto Rossi. |
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12:30- |
Closing |