SPL2014 Tutorials

Tutorial 1

Facultad de Ciencias Exactas y Naturales, UBA

Ciudad Universitaria, Pabellón 1, Aula 8

November, 4^th - Tuesday

09:00h - 12:30

Title: Power-Temperature Basics on FPGA

Eduardo BOEMO

Tutorial Summary: Review of ICs design fundamental for enginners interested on FPGA technology. Special emphasis on speed, power and thermal optimization.

Eduardo BOEMO: Titular Professor, Engineering School, Univ. Autónoma de Madrid. Honorary Professor CAECE University. Ph.D. in Telecom Engineering Univ. Politécnica de Madrid. Electrical Engineer degree, Univ. Nacional de Mar del Plata, Argentine. General Chairperson of IEEE FPL 2006, IEEE SPL (2008, 2007, and 2006 ), and JCRA (2007, 2003). Member IEEE FPL Steering Comm. Associate Editor ACM Trans. on Reconfigurable Systems. More than 100 published works on Area–Time-Power-Thermal Optimization, Synchronization, and E.E. Education.

Tutorial 2

Facultad de Ciencias Exactas y Naturales, UBA

Ciudad Universitaria, Pabellón 1, Aula 5

November, 4^th - Tuesday

15:30h - 18:00

Title: The Art of Designing and Implementing Finite State Machines in Hardware

Volnei A. Pedroni

Tutorial Summary: Very few topics affect a larger audience of digital circuit designers and instructors than the subject of correctly designing and implementing finite state machines (FSMs) in hardware (as opposed to software). Such need is crucial to the development of digital systems, particularly as their complexity grows, and is aggravated by the fact that still only trivial machines can be satisfactorily modeled by current electronic design automation (EDA) tools.
This tutorial is based on a recent publication by MIT Press [1], which is the first work to specifically and extensively investigate and describe the art of completely designing and implementing FSMs in hardware.
The first point discussed is what really differentiates one FSM from another as far as hardware is concerned. It is shown that any FSM falls in one of just three categories (proposed in a new classification), called regular, timed, and recursive finite state machines. This led to the development of three systematic design procedures, allowing any FSM to be easily and optimally implemented in hardware.
Other fundamental hardware aspects are treated subsequently, including state encoding styles, input signals conditioning, multiple clock domains and the use of synchronizers, capture of initial values, the importance of reset, and the construction of safe state machines.
VHDL and SystemVerilog codes for the synthesis of FSMs in all three categories are also presented and discussed.

Volnei A. Pedroni: Short Biography:

Education:

BSc in Electrical Engineering, Federal University of Rio Grande do Sul (UFRGS), 1975.
MSc in Electrical Engineering, California Institute of Technology (CALTECH), 1991.
PhD in Electrical Engineering, California Institute of Technology (CALTECH), 1995.

Work:

Associate Professor at Federal Technological University of Parana State – UTFPR (Brazil).

Visiting appointments:

CALTECH: 2008, 2011, 2013
Harvey Mudd College: 1997, 2009
Università degli Studi di Trento (Italy): 2008, 2010
Jet Propulsion Laboratory (JPL): 1992

Areas or interest/research:

Digital and mixed MOS/VLSI integrated circuits. VHDL- and FPGA-based design and synthesis of digital circuits and systems. Hardware-implemented algorithms for control and communications applications.

Books:

[1] Volnei A. Pedroni, Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog), MIT Press, Dec. 2013.
[2] Volnei A. Pedroni, Circuit Design and Simulation with VHDL, 2nd edition, MIT Press, 2010.
[3] Volnei A. Pedroni, Digital Electronics and Design with VHDL, Elsevier Morgan Kaufmann, 2008.
[4] Volnei A. Pedroni, Circuit Design with VHDL, 1st edition, MIT Press, 2004.