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SPL 2014 Keynotes

Keynote 1

November, 5st - Wednesday
09:30h - 11:00h


Fabless and IP: The opportunity for Latin America

Victor Grimblatt(R&D Group Director and General Manager, Synopsys Chile R&D Center)

Keynote Summary: Since the invention of the transistor in 1947 and the integrated circuit in 1959 the semiconductor business has went through an interesting history starting at companies dedicated to the design and fabrication of their own chips, going through the ASIC business pioneered by VLSI Technology and LSI Logic, and ending at the fabless and IP business. Market needs, semiconductor technology, and EDA have been the drivers of this business changes and the role of electronics in today’s world. This talk will present the semiconductor business and related business since its start to current days, from an historical, technical, and economical point of view. It will focus on the fabless and IP business which are the real opportunities for Latin America. 

Short Bio: He was born in Viña del Mar, Chile. He has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG - France) and an electronic engineering diploma from Universidad Técnica Federico Santa Maria (Chile). Currently, he is R&D Group Director and General Manager of Synopsys Chile, leader in Electronic Design Automation. He opened the Synopsys Chile R&D Center in 2006. Before joining Synopsys, he worked for different Chilean and multinational companies, such as Motorola Semiconductors, Honeywell Bull, VLSI Technology Inc., and Compass Design Automation Inc. He started to work in EDA in 1988 in VLSI Technology Inc. where he developed synthesis tools being one of the pioneers of this new technology. From 2006 to 2008 he was member of the "Chilean Offshoring Committee" organized by the Minister of Economy of Chile. In 2010 he was awarded as "Innovator of the Year in Services Export". In 2012 he was nominated for to best engineer of Chile award. He is also member of several Technical Program Committees on Circuit Design and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He also teaches several courses at Universidad de Chile and Universidad de los Andes related to integrated circuits and Computer Architecture.


Keynote 2

November, 6st - Thursday
09:00h - 10:30h


Configuration of complex FPGA devices

Alfredo de la Cruz (IC Senior Member of Technical Staff Design Engineer at Altera)

Keynote Summary: With new generations of FPGAs becoming extremely complex devices incorporating multi-core CPUs, a myriad of peripheral hardened-IPs and mind-boggling amounts of programmable logic; the configuration of such devices is becoming a true challenge for the overall success of the programmable-technology. FPGA configuration is faced against more-often-than-not conflicting demands as increased security, lower initialization time as well as smaller configuration bitstream sizes. All these requirements are also present during partial reconfiguration, which is a technology rapidly gaining acceptance among different applications environments, adding specific demands associated with the dynamics of the changes to the FPGA-device programming. During this keynote presentation, the author explores the multiple challenges facing the configuration of complex FPGA devices associated with CVP (Configuration Via PCIe), security, bitstream compression and SEU detection. He discusses the relation between CVP and early transceiver calibration within most recent Arria devices. In particular detail he focuses on the deeply cross-encountered requirements associated with partial reconfiguration, both in hardware as well in the CAD software tools, and examine them under the light of the approaches taken by some of the major FPGAs manufacturers, specifically Altera. He also surveys some of the existing solutions from these manufacturers to reduce the bitstream storage demands, associated with either full or partial reconfiguration, and project some possible future directions in these areas for the forthcoming years. 

Short Bio: Alfredo de la Cruz currently works as IC Senior Member of Technical Staff Design Engineer at Altera. He holds his MSc and BSc from the Havana Polytechnic Institute as Microelectronics Engineer and Electronics Engineering, respectively. Since 1995, he pioneered the introduction of patented data/image compression encryption IP-cores in FPGA within European and German companies for 15 years. From 2008 to 2012 he was Director of Electronics and Technology in the leading manufacturer of medical robots METI, introducing the use of FPGA and IP-Cores to catalyze development cycles. In 2012 he joined Altera, where he is currently working in the architecture of the Stratix10, Altera newest generation, in particular architecting the device configuration and bitstream compression.


Keynote 3

November, 6st - Thursday
14:00h - 15:30h


Unlocking FPGAs Using High-Level Synthesis Compiler Technologies

Fernando Martinez Vallina (Senior Staff Software Engineer at Xilinx)

Keynote Summary: FPGA devices have long been the standard for massively parallel computing fabrics with a low power footprint. Unfortunately, the complexity associated with an FPGA design has limited the rate of adoption by software application programmers. Recent advances in compiler and FPGA fabric capabilities are reversing this trend and there is a growing adoption of FPGAs for algorithmic workloads such as data analytics, feature detection in images, adaptive beam forming, etc. One of the pillars of this shift is the Vivado HLS compiler, which enables the compilation of algorithms captured in C and C++into efficient FPGA implementations. This talk focuses on how the HLS compiler creates algorithm specific compute architectures and removes the constraints designers face when dealing with fixed parallel architectures such as multi-core CPUs/GPUs. . 

Short Bio: Fernando Martinez Vallina currently works as a Senior Staff Software Engineer at Xilinx. He holds a Ph.D from the Illinois Institute of Technology. Since 2007, he has been working on research and development of compilers for synthesizing C and C++ programs into efficient RTL designs for both ASIC and FPGA implementation. In 2011, he joined Xilinx as part of the acquisition of AutoESL Design Technologies. He is currently working on the Vivado HLS compiler to enable more software engineers to run their code on Xilinx FPGA devices.