This workshop will guide through the process of using Vivado and IP Integrator to create a complete ARM Cortex-A9 based processor system targeting the ZedBoard Board. The Zynq SoC-FPGA is the core of the ZedBoard. Both, the PL and the PS parts will be described and used. You will use the Block Design feature of the IP Integrator to add and configure the PS7 and IP Cores to create the hardware system within the Vivado environment and then export the system to the VITIS tools. In VITIS a software application project will be created by writing the respective 'C' code. In the last lab, a FreeRTOS application project will be created. All the projects will be implemented on ZedBoards.

• Get familiar with Vivado-Vitis design flow for the Zynq SoC-FPGA.
• Configure PS7
• Create block diagram system and export it to Vitis
• Add Xilinx standard IP into the PL
• Use of Inputs and Outputs hardware available in the ZedBoard.
• Create a software application project in VITIS, ‘C’ code-based
• Generate and configure a FreeRTOS BSP
• Write a simple FreeRTOS application
• Use the ZedBoard to test the functionality of the projects

It would be useful to have some knowledge on FPGA architecture, as well as basic VHDL or Verilog understanding. Familiarity with the 'C' programming language is required.

The evolution of reconfigurable computing in recent decades following Moore's law was impressive. Xilinx (now AMD) was the inventor of the FPGA back in the early 80s, later introduce Adaptable SoC (system on a chip) and recently the ACAP (Adaptive Computing Acceleration Platform) architecture.

RTL code-based programming for FPGAs has evolved into new high-level paradigms that allow increasing the level of abstraction and addressing even more complex problems using Cloud Computing FPGA accelerators.

This tutorial will introduce the Vitis Unified Software Platform environment for developing FPGA accelerators. Vitis environment enables the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems. Vitis supports: C and C++ kernels. RTL design flows are also supported for experienced hardware developers. Each of these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source accelerated libraries.

• AMD-Xilinx Platforms Introduction
• Intro to Vitis for Acceleration Platforms
• Vitis Tool Flow and Open CL Execution Model
• Vitis Design Analysis and Methodology
• Host Code Optimization
• Kernel Optimization
• Vitis Accelerated Libraries
• Vitis hardware debug
• Vitis RTL kernels Accelerated Libraries
• PYNQ for Compute Acceleration

The labs will provide hands-on experience using Vitis with AMD-Xilinx FPGA hardware. You will learn how to develop applications using the Vitis development environment that supports OpenCL/C/C++ and RTL kernel to deploy on premise or in the cloud. The complete set of labs includes the following modules:

1. Introduction to Vitis Part 1: This lab shows you how to use the Vitis GUI to create a new project using a simple vector addition example.
2. Introduction to Vitis Part 2: In this lab you will continue with the previous example and run hardware emulation (hw_emu) to verify the functionality of the generated hardware design and profile the whole application. You will then use AWS F1 or on-premise hardware to validate the design.
3. Improving Performance: This lab shows how bandwidth can be improved, and thus system performance, by using wider data path and transferring data in parallel using multiple memory banks.
4. Optimization: This lab guides you through the steps to analyse various generated reports and then apply optimization techniques, such as DATAFLOW on the host program and PIPELINING on kernel side to improve throughput and data transfer rate.
5. Vision Lab: In this lab you will create a Vitis design using the command line. The design uses two kernels from the Vitis Accelerated Libraries, image resize and image resize & blur. You will run software emulation and test the kernels in hardware.
6. PYNQ Labs: In this series of labs you will learn how to use PYNQ for easier user of Xilinx compute acceleration platforms.

Some basic FPGA awareness would be an advantage, but is not required, although participants should have some knowledge of parallel processing concepts and/or parallel hardware. Familiarity with the C/C++ programming language is required.

AMD/Xilinx will provide remote access to cloud instances, which will be enabled with Xilinx tools and devices. Attendees must have their own laptop with reasonable screen size to effectively use the required software. (Tablet, and Netbook type devices are not suitable.). The organizer will provide a limitrd number of PC to access to the tools.

This tutorial will briefly introduce the heterogeneous Versal Adaptive Compute Acceleration Platform. We will primarily focus on the Adaptable Intelligent Engine (AIE) a new type of compute element in the latest Xilinx technology. The AI Engine is a tiled array of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provide high compute density.

We will describe the AI Engine tile and AI Engine array architecture as well as the different data movement alternatives. We will also introduce the AI Engine programming model, which consists of a Data Flow Graph Specification written in C++ and the kernel description written either in C or C++. The application can be compiled and executed using the AI Engine tool chain, which is part of the Vitis Unified Software.

• Versal ACAP Architecture
• Versal AI Engine Memory and Data Movement
• Versal AI Engine Architecture
• Scalar and Vector data types
• Windows and Streaming Data types
• Vitis tool flow for AI Engine
• The AI Engine programming model
• AI Engine Design Analysis
• Optimized open sources libraries for the AI Engine

Some basic FPGA awareness would be an advantage, but is not required, although participants should have some knowledge of parallel processing concepts and/or parallel hardware. Familiarity with the C++ programming language is required (templates and classes). Familiarity with fix point arithmetic will be and advantages. Familiarity Vitis IDE software for application acceleration development flow will be an advantage

AMD/Xilinx will provide remote access to cloud instances which will be enabled with Xilinx tools and devices. Attendees must have their own laptop with reasonable screen size to effectively use the required software. (Tablet, and Netbook type devices are not suitable.)