Program


Workshops

Sunday, April 7
09:00 - 12.30 Workshop AWS F1 - Part I
FPGA-based Accelerated Cloud Computing with AWS EC2 F1 and SDAccel
Venue: CADIEEL - Avda. Córdoba 950 4th Floor.

Map Location

Coffe Break:

10.30 - 11.00

14:00 - 17:00 Workshop AWS F1 - Part II
FPGA-based Accelerated Cloud Computing with AWS EC2 F1 and SDAccelbr
Venue: CADIEEL - Avda. Córdoba 950 4th Floor.

Map Location

Coffe Break:

15.30 - 16.00

Monday, April 8
08:00 - 12.30 Workshop PYNQ - Part I
PYNQ: Python Productivity for Zynq
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

10.30 - 11.00

09:00 - 12.30 Workshop SDSoC & HLS - Part I
FPGA SoC design from a higher level of abstraction: SDSoC and HLS
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

10.30 - 11.00

14:00 - 16.00 Workshop PYNQ - Part II
PYNQ: Python Productivity for Zynq
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

15.30 - 16.00

14:00 - 17.00 Workshop SDSoC & HLS - Part II
FPGA SoC design from a higher level of abstraction: SDSoC and HLS
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

15.30 - 16.00

Tuesday, April 9
09:00 - 12.30 Workshop COCOTB - Part I
Testbenchs in Python: COCOTB
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

10.30 - 11.00

Workshop SDSoC & HLS - Part III
FPGA SoC design from a higher level of abstraction: SDSoC and HLS
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

10.30 - 11.00

14:00 - 17.00 Workshop COCOTB - Part II
Testbenchs in Python: COCOTB
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

15.30 - 16.00

Workshop SDSoC & HLS - Part IV
FPGA SoC design from a higher level of abstraction: SDSoC and HLS
Venue: CC Borges - Viamonte and San Martín

Map Location

Coffe Break:

15.30 - 16.00

Conference

Wednesday, April 10
08:30 - 09.00 Conference Registration
09:00 - 09.30 Opening
09:30 - 10.30 Keynote: FPGA Prospectives, From Advanced Instrumentation Towards Supercomputing
Andrés Cicuttin - International Centre for Theoretical Physics
10:30 - 11.00 Coffe Break
11:00 - 12.40 Paper Session: W1 - Networking and Connectivity
Study of the data exchange between Programmable Logic and Processor System of Zynq-7000 devices (Rodrigo Melo, INTI)
Towards 100 GbE FPGA-based Flow Monitoring (Tobias Alonso, UAM)
High-Speed serial protocol multi-link and multi-stage for FPGAs (David Caruso, Satellogic)
Serial QDR LVDS High-Speed ADCs on Xilinx Series 7 FPGAs (Bruno Valinoti, INTI)
12:40 - 14.00 Lunch
14:00 - 15.15 Keynote: Some Key Trends in the Networked use of FPGAs
Gustavo Sutter - Universidad Autonoma de Madrid
15:15 - 15.45 Coffe Break
15:45 - 17.00 Paper Session: W2 - Design Tools and Methodology
Design, simulation, implementation and testing of search and tracking modules for a FPGA-based GPS receiver (Facundo Larosa, UTN-FRH)
Flexible Software to Hardware migration methodology for FPGA design and verification (Ricardo Cayssials, UTN-FRBB/UNS)
Design for Portability of Reconfigurable Instrumentation Based on Programmable Systems-on-Chip (Andrés Cicuttin, ICTP)
Thursday, April 11
08:30 - 09.00 Conference Registration
09:00 - 10.00 Keynote: IoT - opportunities and challenges for the Region
Victor Grimblatt - Synopsys
10:00 - 11.00 Coffe Break + Poster Session
11:00 - 12.40 Paper Session: T1A - Medical Applications T1A - Medical Applications
A low power FPGA based control unit for an implantable neuromodulation circuit (Santiago Martínez, UDELAR)
Hardware implementation of a multi-channel EEG lossless compression algorithm (Federico Favaro, UDELAR)
Paper Session: T1B - Nuclear Applications
FPGA Based Wide Range Neutron Flux Monitoring System using Campbell Mode (Juan Alarcón, CNEA)
Digital count-rate meter and flux-change-rate meter with automatic adjust of counting time based on FPGA for pulse-mode flux measurements in nuclear reactors (Gloria Ríos, CNEA)
12:40 - 14.00 Lunch
14:00 - 15.15 Keynote: Dynamic Partial Reconfiguration
Julio Daniel Dondo - Universidad de Castilla-La Mancha / Universidad Nacional de San Luis
15:15 - 15.45 Coffe Break
15:45 - 17.00 Paper Session: T2 - Computer Vision and Graphics
A Real Time Adaptive Template Matching Algorithm in UAV Navigation Using a SoC System (Alex Gonçalves, ITA)
Implementation of search process for a content based image retrieval application on System on Chip (Romina Molina, UNSL)
A Proposal of Two Histogram Circuits to Calculate Similarities between Video Frames using FPGAs (Eduardo Boemo, UAM)
Friday, April 12
08:30 - 09.00 Conference Registration
09:00 - 10.00 Keynote: Pipelining Fundamentals in FPGA
Eduardo Boemo - Universidad Autónoma de Madrid
10:00 - 11.00 Coffe Break + Poster Session
11:00 - 12.40 Keynote: Pipelining Fundamentals in FPGA
Eduardo Boemo - Universidad Autónoma de Madrid
12:40 - 14.00 Lunch
14:00 - 14.50 Paper Session: F1 - Arithmetic Applications
An Application of the Hardened Floating-Point Cores on HIL Simulations (Elías Todorovich, UNICEN)
High-Performance Architectures for Finite Field Inversion over GF ( 2^163 ) (Guillermo David-Nuñez, UNIAJC)
14:50 - 15.15 Finish