NOTE: Oral presentation are scheduled as 20 MINUTES plus 5 MINUTES for questions.
Monday 26
| 08:00 | Registration |
| 09:00 | SPL 2007 Inauguration and Plenary Conference: "Taking Engineering Education to the Next Level", Sandra Larrabee, Synplicity Inc. |
| 10:00 | Poster Session 1 / Coffee break |
| 11:00 | Session M1: DSP, Chairperson: Eduardo de la Torre FPGA Neural Networks Implementation for Nuclear Pulses Parameters Estimation Genomic Microarray Processing on a FPGA for Portable Remote Applications TIP-TILT Mirror Control Based on FPGA for an Adaptive Optics System |
| 12:15 | Lunch |
| 14:15 | Session M2: Computer Arithmetic, Chairperson: TBD FPGA implementation of base-N logarithm Memory optimized architecture for efficient Gauss-Jordan matrix inversion Efficient Hardware Implementations for Gaussian Normal Basis Multiplication Over GF (2163) |
| 15:30 | Coffee break |
| 16:00 | Session M3: On-Chip Interconnections, Chairperson: TBD A Buffered Crossbar-Based Chip Interconnection Architecture Supporting Quality of Service Quantitative comparison of switching strategies for Networks on Chip Fast Placement-intact Logic Perturbation Targeting for FPGA Performance Improvement A novel Reconfigurable Architecture for Temporal and Spatial Application Mapping |
| 17:40 | End of sessions |
Tuesday 27
| 08:45 | Plenary Conference: Al Simon, Actel Corp. |
| 09:45 | Poster Session 2 / Coffee break |
| 10:45 | Session T1: Hw-Sw Co-Design, Chairperson: TBD FPGA-Based acceleration of fingerprint minutiae matching Extending Embedded Computing Scheduling Algorithms for Reconfigurable Computing Systems Towards Fine and Medium Grain Dynamic Functional Extraction for Hw/Sw Acceleration |
| 12:00 | Lunch |
| 14:00 | Session T2: High-Level Languages & Embedded Processors, Chairperson: TBD Comparative Analysis of High Level Programming for Reconfigurable Computers: Methodology and Empirical Study A FPGA-Based Mobile Robot Controller Tcl/Tk for EDA Tools |
| 15:20 | |
| 16:20 | Session T3: IP Cores, Chairperson: TBD A System for Fast Text-to-Braille Translation Based on FPGAs A Hardware Based Braille Note Taker High Resolution Pulse Width Modulators in FPGA Digital Signature Embedding Technique for IP Core Protection |
| 18:00 | End of sessions |
| 20:30 | Gala Dinner |
Wednesday 28
| 08:30 | Plenary Conference: "Structured ASICs/ Silicon Platforms enabling quick time to market solutions while mitigating risk"Steve Farrell, Sales Manager , CHIPX Corp. USA |
| 09:30 | |
| 10:15 | Session W1: Vision & Video, Chairperson: TBD Hardware Architectures for Adaptive Background Modelling An Area Cost Optimized Fast Parallel Label Assignment VLSI Architecture FPGA Based Design of CAVLC and EXP-GOLOMB Coders for H.264/AVC Baseline Entropy Coding |
| 11:30 | Concluding Remarks and Awards |
| 12:00 | End of Conference |
Monday 26th
Poster Session 1 (10:00-11:00)
85. An Efficient Scalable Parallel Hardware Architecture For Multilayer Spiking Neural Networks
Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil
National Institute for Astrophysics, Optics and Electronics, Mexico65. Low Power AMR System Based on FPGA
Nagore Benitez, Nestor Ayuso, Gonzalo Bellanco, Carlos Amuchastegui, Gonzalo Alvarez, Igor Laniella, Hodei Cepeda, Alfonso Guerendiain
University of the Basque Country, Kifer Computer Science Services, Spain15. A genetic algorithm based solution for dynamically reconfigurable modules allocation
Vincenzo Rana, Chiara Sandionigi, Marco Santambrogio
Politecnico di Milano16. A low cost, FPGA based, Video Streaming Server
Graeme Stewart, David Renshaw, Martyn Riley
Institute for System Level Integration, UK, Edinburgh University, 4i2i Communications Ltd, UK34. Development of Block-Cipher Library for Reconfigurable Computers
Miaoqing Huang, Tarek El-Ghazawi, Brian Larson, Kris Gaj
The George Washington University, Silicon Graphics, Inc., USA, George Mason University44. AES-128 Cipher. High Speed, Low Cost FPGA Implementation
Mónica Liberatori, Fernando Otero, Juan Carlos Bonadero, Jorge Castiñeira
Universidad Nacional de Mar del Plata84. Soft Error Tolerant Carry-Select Adders Implemented into Altera FPGAS
Eduardo Mesquita, Helen Franck, Luciano Agostini, José Güntzel
Universidade Federal de Pelotas95. A Reconfigurable FPGA-Based Architecture for Modular Nodes in Wireless Sensor Networks
Jorge Portilla, Angel de Castro, Teresa Riesgo
Universidad Politecnica de Madrid
Tuesday 27th
Poster Session 2 (09:45-10:45)
50. FPGA-based platform for image and video processing embedded systems
Fco. Javier Toledo Moreo, J. Javier Martínez Alvarez, J. Manuel Ferrandez Vicente
Univ. Politecnica de Cartagena11. FPGA Modulator for Matrix Converter
Martin González, Marcos Funes, Roberto Petrocelli, Mario Benedetti
Universidad Nacional de Mar del Plata40. Viability study of soft-processor usage for electronic collimation control in medical applications
Estanislao Aguayo, Rubén Martín, Gustavo Sutter, Eduardo Boemo
CIEMAT - Electronics Division, Spain, Universidad Autónoma de Madrid42. Merging FPGA and FPAA Reconfiguration Capabilities for IEEE 1451.4 Compliant Smart Sensor Applications
Diego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos
Univesity of Granada61. A novel hardware/software codesign methodology based on dynamic reconfiguration with ImpulseC and CoDeveloper
Anna Antola, Marco Fracassi, Pamela Gotti, Chiara Sandionigi, Marco Santambrogio
Politecnico di Milano66. Execution of algorithms using a Dynamic Dataflow Model for Reconfigurable Hardware - Commands in Dataflow Graph
Vitor Astolfi, Jorge Silva
University of Sao Paulo88. Compact FPGA-based systolic array architecture for motion estimation using full search block matching
Griselda Saldaña, Miguel Arias
National Institute for Astrophysics, Optics and Electronics, Mexico22. Bus Decryption Overhead Minimization with Code Compression
Eduardo Wanderley, Guy Gogniat, Jean-Philipe Diguet
CEFETRN, Brazi, UBS, France14. Comparative Analysis of Multitasking Scheduling Algorithms for Reconfigurable Computing regarding Context Switches and Configuration Cache Usage
Christopher Spies, Leandro Soares Indrusiak, Manfred Glesner
Darmstadt University of Technology90. AxB is different of BxA in terms of power consumption: Some Examples on FPGAs
Eduardo Boemo, Gustavo Sutter
Universidad Autónoma de MadridDesigner Forum 1 (15:20-16:20)
Optimal Technology Mapping for Heterogeneous FPGA Using Genetic Algorithm
T.P. Hashir, K.K. Ajayan
Trivandrum College of EngineeringMultiobjective Optimization for the Circuit Partitioning Problem into Multiple Devices
Ramón González, Benjamín Barán, J. Ignacio Hidalgo
Universidad Católica de Asunción, Universidad Complutense de MadridTools and Techniques for Safe Synthesis of FSMDs Represented in Behavioral Level Implicit Style Verilog HDL or VHDL
Shahriyar M. Rizvi, Jerry J. Cupal, Tawhidul I. Chowdhury, Khalid Mahmood
American International University-Bangladesh , University of Wyoming, Daffodil Group Ltd.El Modelo Computacional en Diseño de Sistemas Digitales Heterogéneos
Jorge R. Osio, José A. Rapallini
Universidad Nacional de La PlataColor Digital Video Acquisition and Processing System Using Reconfigurable Logic
Emerson C. Pedrino, Valentin O. Roda, Lucio Jorge , Carlos A. De Francisco
Universidade de São Paulo, Centro Universitário Central Paulista/UNICEPArquitetura para Crescimento de Regiões de Imagens Binárias
Emerson C. Pedrino, Marcelo Marinho, Valentin O. Roda, Osmar Ogasawara
Universidade de São PauloA Motion Compensation Architecture Design and Prototyping Targeting SDTV Frames for H.264/AVC Standard
Fabiane Rediess, José Güntzel, Luciano Agostini, Sergio Bampi
Universidade Federal de Pelotas, Universidade Federal do Rio Grande do SulA General Model for Common Hardware Reconfiguration Techniques and their
Optimization
Heiko Hinkelmann, Kai Groneberg, Manfred Glesner
Darmstadt University of TechnologyUn Controlador Inteligente para la Reconfiguracion Remota de Circuitos Lógicos Reprogramables
Fernando I. Szklanny, Elio A. De María, Carlos E. Maidana, Edgardo Gho
Universidad Nacional de La MatanzaUna Metodología para el Diseño Digital en el Nivel Preuniversitario
Arturo J. Miguel de PriegoTarjeta de Diseño Abierto para Desarrollo y Educación
Diego J. Brengi, Salvador E. Tropea, Juan P. D. Borgna
Instituto Nacional de Tecnología IndustrialDiseño e Implementación de un Microprocesador con Arquitectura Segmentada en FPGA
José Alberto Díaz García, Adolfo Méndez Madrigal, Miguel Angel Aguilar Ulloa
Instituto Tecnológico de Costa Rica
Wednesday 28th
Plenary Conference (9:00 to 9:50)
Presentation Title: Structured ASICs/ Silicon Platforms enabling quick time to market solutions while mitigating risk.
Steve Farrell, Sales Manager , CHIPX Corp. USA
Summary: Presentation will overview the capabilities of ChipX as a fabless semiconductor company providing a full range of ASIC platforms and services. These ASIC capabilities provide a quick time to marketing implementation which mitigates design risk and provides the flexibility that lowers the overall cost of ownership. Topics included are:
- Benefits of the Structured ASIC approach
- Comparison of FPGAs to various ASIC platforms
- FPGA cost reduction using ChipX
- Risk mitigation to larger SOC developments
- Conversion from FPGA prototypes to ASICs
- Overview of Process Technologies
- Flexibility of Synthesizable IP
Designer Forum 2 (9:30-10:15)
Hardware Accelerators for the Microblaze Software Embedded Processor
Manuel Hernández Calviño, José Ignacio Benavides Benítez, Sergio R. Geninatti, Francisco Javier Hórmigo Aguilar, Julio Villalba Moreno
Universidad de La Habana, Universidad de Córdoba, Universidad de Rosario, Universidad de MálagaRoadRunner and IPGen: A Combined Solution to Speedup Configurable Systems Design
C. Bolchini, C. Brandolese, L. Frigerio, V. Rana, F. Salice, M. Santambrogio
Politecnico di MilanoA HW/SW Co-Design Platform for the URT51 Real-Time Processor
Martin Duval, Ricardo Cayssials, Edgardo Ferro, Omar Alimenti
Universidad Nacional del SurAnalisys and FPGA Implementation of Combined Error-Control and Encryption Schemes
Leonardo Arnone, Carlos Gayoso, Claudio González, Jorge Castiñeira Moreira, Mónica Liberatori
Universidad Nacional de Mar del PlataInterfase dedicada compatible con Red Ethernet
María Isabel Schiavon, Daniel Crepaldo
Universidad Nacional de RosarioAdministrador de Paquetes para Capa de Protocolo USB 2.0
Diego E. Costa, Esteban M. Peláez, Carlos F. Sosa Páez, Héctor Vellón
Universidad Nacional de San LuisA Soft Core for Pattern Recognition
Coral González-Concejero, Victoria Rodellar, Agustin Álvarez-Marquina, Elvira Martínez de Icaya, Pedro Gómez-Vilda
Universidad Politécnica de MadridDiseño e Implementación de una Unidad de Funciones Matemáticas
José Alberto Díaz García, Eugenio Salazar Brenes
Instituto Tecnológico de Costa RicaDiseño de Aceleradores para el Alineamiento Global de Secuencias de ADN
Martin A. Lozano, Vladimir Trujillo-Olaya, Jaime Velasco-Medina
Universidad del Valle