Preliminary Technical Program

NOTE: Oral presentation are scheduled as 20 MINUTES plus 5 MINUTES for questions.

Monday 26

08:00

Registration

09:00

SPL 2007 Inauguration and Plenary Conference: "Taking Engineering Education to the Next Level", Sandra Larrabee, Synplicity Inc.

10:00

Poster Session 1 / Coffee break

11:00

Session M1: DSP, Chairperson: Eduardo de la Torre

FPGA Neural Networks Implementation for Nuclear Pulses Parameters Estimation
Daniel Sebastián Estryk, Gloria Elisa Rios, Claudio Abel Verrastro
Comisión Nacional de Energía Atómica

Genomic Microarray Processing on a FPGA for Portable Remote Applications
V. Rodellar, Francisco Diaz, Raul Malutan, P. Gómez, Rafael Martinez, Eduardo Garcia Rico, Jesus Pelaez
Universidad Politecnica de Madrid

TIP-TILT Mirror Control Based on FPGA for an Adaptive Optics System
Fernando Gago Rodríguez, Luis Fernando Rodríguez Ramos, Guillermo Herrera Carlés, José Vicente Gigante, Ángel Alonso, Teodora Viera, Juanjo Piqueras, José Javier Díaz García
Instituto de Astrofísica de Canarias

12:15

Lunch

14:15

Session M2: Computer Arithmetic, Chairperson: TBD

FPGA implementation of base-N logarithm
Salvador Tropea
Instituto Nacional de Tecnología Indrustrial, Argentina

Memory optimized architecture for efficient Gauss-Jordan matrix inversion
Goncalo M. de Matos, Horacio C. Neto
Technical University of Lisbon

Efficient Hardware Implementations for Gaussian Normal Basis Multiplication Over GF (2163)
Vladimir Trujillo, Jaime Velasco-Medina, Julio Cesar Lopez
Universidad del Valle, Universidad de Campinas

15:30

Coffee break

16:00

Session M3: On-Chip Interconnections, Chairperson: TBD

A Buffered Crossbar-Based Chip Interconnection Architecture Supporting Quality of Service
George Kornaros, Yannis Papaefstathiou
Technical University of Crete

Quantitative comparison of switching strategies for Networks on Chip
Anthony Leroy, Julien Picalausa, Dragomir Milojevic, Frederic Robert , Diederik Verkest
Université Libre de Bruxelles

Fast Placement-intact Logic Perturbation Targeting for FPGA Performance Improvement
Catherine L. Zhou, Wai-Chung Tang, Yu-Liang Wu
The Chinese University of Hong Kong

A novel Reconfigurable Architecture for Temporal and Spatial Application Mapping
Alexander Danilin, Sergei Sawitzki
NXP Semiconductors Research, The Netherlands

17:40

End of sessions

 

Tuesday 27

08:45

Plenary Conference: Al Simon, Actel Corp.

09:45

Poster Session 2 / Coffee break

10:45

Session T1: Hw-Sw Co-Design, Chairperson: TBD

FPGA-Based acceleration of fingerprint minutiae matching
Almudena Lindoso, Luis Entrena, Juan Izquierdo
University Carlos III of Madrid

Extending Embedded Computing Scheduling Algorithms for Reconfigurable Computing Systems
Proshanta Saha, Tarek El-Ghazawi
The George Washington University

Towards Fine and Medium Grain Dynamic Functional Extraction for Hw/Sw Acceleration
Vladimir Matev, Eduardo De la Torre, Teresa Riesgo
Universidad Politécnica de Madrid

12:00

Lunch

14:00

Session T2: High-Level Languages & Embedded Processors, Chairperson: TBD

Comparative Analysis of High Level Programming for Reconfigurable Computers: Methodology and Empirical Study
Esam ElDin El-Araby, Mohamed Taher, Mohamed Abouellail, Tarek El-Ghazawi, Gregory Newby
The George Washington University, Arctic Region Supercomputing Center, USA

A FPGA-Based Mobile Robot Controller
Denis Wolf, Jose Holanda, Vanderlei Bonato, Rafael Peron, Eduardo Marques
University of Sao Paulo

Tcl/Tk for EDA Tools
Elías Todorovich, Oswaldo Cadenas
Universidad Autónoma de Madrid, The University of Reading

15:20

Designer Forum 1

16:20

Session T3: IP Cores, Chairperson: TBD

A System for Fast Text-to-Braille Translation Based on FPGAs
Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray
Curtin University of Technology, Australia

A Hardware Based Braille Note Taker
Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray
Curtin University of Technology, Australia

High Resolution Pulse Width Modulators in FPGA
Angel de Castro, Gustavo Sutter, Santa Concepcion Huerta, José Antonio Cobos
Universidad Autonoma de Madrid, Universidad Politecnica de Madrid

Digital Signature Embedding Technique for IP Core Protection
Encarnación Castillo, Antonio García, Uwe Meyer-Baese, Luis Parrilla, Diego P. Morales, Antonio Lloris
University of Granada, Florida State University

18:00

End of sessions

20:30

Gala Dinner

 

Wednesday 28

08:30

Plenary Conference: "Structured ASICs/ Silicon Platforms enabling quick time to market solutions while mitigating risk"Steve Farrell, Sales Manager , CHIPX Corp. USA

09:30

Designer Forum 2

10:15

Session W1: Vision & Video, Chairperson: TBD

Hardware Architectures for Adaptive Background Modelling
Matti Juvonen, Jose Gabriel de Figueiredo Coutinho, Wayne Luk
Imperial College London

An Area Cost Optimized Fast Parallel Label Assignment VLSI Architecture
Gustavo Fernando Dessbesell, Márcio Alexandre Pacheco, João Baptista dos Santos Martins, Rolf Fredi Molz
Federal University of Santa Maria, University of Santa Cruz do Sul

FPGA Based Design of CAVLC and EXP-GOLOMB Coders for H.264/AVC Baseline Entropy Coding
Thaísa Silva, João Vortmann, Luciano Agostini, Sergio Bampi, Altamiro Susin
Federal University of Pelotas, Federal University of Rio Grande do Sul

11:30

Concluding Remarks and Awards

12:00

End of Conference

 

Monday 26th

Poster Session 1 (10:00-11:00)

85. An Efficient Scalable Parallel Hardware Architecture For Multilayer Spiking Neural Networks
      Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil
      National Institute for Astrophysics, Optics and Electronics, Mexico

65. Low Power AMR System Based on FPGA
      Nagore Benitez, Nestor Ayuso, Gonzalo Bellanco, Carlos Amuchastegui, Gonzalo Alvarez, Igor Laniella, Hodei Cepeda, Alfonso Guerendiain
      University of the Basque Country, Kifer Computer Science Services, Spain

15. A genetic algorithm based solution for dynamically reconfigurable modules allocation
      Vincenzo Rana, Chiara Sandionigi, Marco Santambrogio
      Politecnico di Milano

16. A low cost, FPGA based, Video Streaming Server
      Graeme Stewart, David Renshaw, Martyn Riley
      Institute for System Level Integration, UK, Edinburgh University, 4i2i Communications Ltd, UK

34. Development of Block-Cipher Library for Reconfigurable Computers
      Miaoqing Huang, Tarek El-Ghazawi, Brian Larson, Kris Gaj
      The George Washington University, Silicon Graphics, Inc., USA, George Mason University

44. AES-128 Cipher. High Speed, Low Cost FPGA Implementation
      Mónica Liberatori, Fernando Otero, Juan Carlos Bonadero, Jorge Castiñeira
      Universidad Nacional de Mar del Plata

84. Soft Error Tolerant Carry-Select Adders Implemented into Altera FPGAS
      Eduardo Mesquita, Helen Franck, Luciano Agostini, José Güntzel
      Universidade Federal de Pelotas

95. A Reconfigurable FPGA-Based Architecture for Modular Nodes in Wireless Sensor Networks
      Jorge Portilla, Angel de Castro, Teresa Riesgo
      Universidad Politecnica de Madrid

 

Tuesday 27th

Poster Session 2 (09:45-10:45)

50. FPGA-based platform for image and video processing embedded systems
      Fco. Javier Toledo Moreo, J. Javier Martínez Alvarez, J. Manuel Ferrandez Vicente
      Univ. Politecnica de Cartagena

11. FPGA Modulator for Matrix Converter
      Martin González, Marcos Funes, Roberto Petrocelli, Mario Benedetti
      Universidad Nacional de Mar del Plata

40. Viability study of soft-processor usage for electronic collimation control in medical applications
      Estanislao Aguayo, Rubén Martín, Gustavo Sutter, Eduardo Boemo
      CIEMAT - Electronics Division, Spain, Universidad Autónoma de Madrid

42. Merging FPGA and FPAA Reconfiguration Capabilities for IEEE 1451.4 Compliant Smart Sensor Applications
      Diego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos
      Univesity of Granada

61. A novel hardware/software codesign methodology based on dynamic reconfiguration with ImpulseC and CoDeveloper
      Anna Antola, Marco Fracassi, Pamela Gotti, Chiara Sandionigi, Marco Santambrogio
      Politecnico di Milano

66. Execution of algorithms using a Dynamic Dataflow Model for Reconfigurable Hardware - Commands in Dataflow Graph
      Vitor Astolfi, Jorge Silva
      University of Sao Paulo

88. Compact FPGA-based systolic array architecture for motion estimation using full search block matching
      Griselda Saldaña, Miguel Arias
       National Institute for Astrophysics, Optics and Electronics, Mexico

22. Bus Decryption Overhead Minimization with Code Compression
      Eduardo Wanderley, Guy Gogniat, Jean-Philipe Diguet
      CEFETRN, Brazi, UBS, France

14. Comparative Analysis of Multitasking Scheduling Algorithms for Reconfigurable Computing regarding Context Switches and Configuration Cache Usage
      Christopher Spies, Leandro Soares Indrusiak, Manfred Glesner
      Darmstadt University of Technology

90. AxB is different of BxA in terms of power consumption: Some Examples on FPGAs
      Eduardo Boemo, Gustavo Sutter
      Universidad Autónoma de Madrid

Designer Forum 1 (15:20-16:20)

Optimal Technology Mapping for Heterogeneous FPGA Using Genetic Algorithm
T.P. Hashir, K.K. Ajayan
Trivandrum College of Engineering

Multiobjective Optimization for the Circuit Partitioning Problem into Multiple Devices
Ramón González, Benjamín Barán, J. Ignacio Hidalgo
Universidad Católica de Asunción, Universidad Complutense de Madrid

Tools and Techniques for Safe Synthesis of FSMDs Represented in Behavioral Level Implicit Style Verilog HDL or VHDL
Shahriyar M. Rizvi, Jerry J. Cupal, Tawhidul I. Chowdhury, Khalid Mahmood
American International University-Bangladesh , University of Wyoming, Daffodil Group Ltd.

El Modelo Computacional en Diseño de Sistemas Digitales Heterogéneos
Jorge R. Osio, José A. Rapallini
Universidad Nacional de La Plata

Color Digital Video Acquisition and Processing System Using Reconfigurable Logic
Emerson C. Pedrino, Valentin O. Roda, Lucio Jorge , Carlos A. De Francisco
Universidade de São Paulo, Centro Universitário Central Paulista/UNICEP

Arquitetura para Crescimento de Regiões de Imagens Binárias
Emerson C. Pedrino, Marcelo Marinho, Valentin O. Roda, Osmar Ogasawara
Universidade de São Paulo

A Motion Compensation Architecture Design and Prototyping Targeting SDTV Frames for H.264/AVC Standard
Fabiane Rediess, José Güntzel, Luciano Agostini, Sergio Bampi
Universidade Federal de Pelotas, Universidade Federal do Rio Grande do Sul

A General Model for Common Hardware Reconfiguration Techniques and their
Optimization

Heiko Hinkelmann, Kai Groneberg, Manfred Glesner
Darmstadt University of Technology

Un Controlador Inteligente para la Reconfiguracion Remota de Circuitos Lógicos Reprogramables
Fernando I. Szklanny, Elio A. De María, Carlos E. Maidana, Edgardo Gho
Universidad Nacional de La Matanza

Una Metodología para el Diseño Digital en el Nivel Preuniversitario
Arturo J. Miguel de Priego

Tarjeta de Diseño Abierto para Desarrollo y Educación
Diego J. Brengi, Salvador E. Tropea, Juan P. D. Borgna
Instituto Nacional de Tecnología Industrial

Diseño e Implementación de un Microprocesador con Arquitectura Segmentada en FPGA
José Alberto Díaz García, Adolfo Méndez Madrigal, Miguel Angel Aguilar Ulloa
Instituto Tecnológico de Costa Rica

 

Wednesday 28th

Plenary Conference (9:00 to 9:50)

Presentation Title: Structured ASICs/ Silicon Platforms enabling quick time to market solutions while mitigating risk.

Steve Farrell, Sales Manager , CHIPX Corp. USA

Summary: Presentation will overview the capabilities of ChipX as a fabless semiconductor company providing a full range of ASIC platforms and services. These ASIC capabilities provide a quick time to marketing implementation which mitigates design risk and provides the flexibility that lowers the overall cost of ownership. Topics included are:

 

Designer Forum 2 (9:30-10:15)

Hardware Accelerators for the Microblaze Software Embedded Processor
Manuel Hernández Calviño, José Ignacio Benavides Benítez, Sergio R. Geninatti, Francisco Javier Hórmigo Aguilar, Julio Villalba Moreno
Universidad de La Habana, Universidad de Córdoba, Universidad de Rosario, Universidad de Málaga

RoadRunner and IPGen: A Combined Solution to Speedup Configurable Systems Design
C. Bolchini, C. Brandolese, L. Frigerio, V. Rana, F. Salice, M. Santambrogio
Politecnico di Milano

A HW/SW Co-Design Platform for the URT51 Real-Time Processor
Martin Duval, Ricardo Cayssials, Edgardo Ferro, Omar Alimenti
Universidad Nacional del Sur

Analisys and FPGA Implementation of Combined Error-Control and Encryption Schemes
Leonardo Arnone, Carlos Gayoso, Claudio González, Jorge Castiñeira Moreira, Mónica Liberatori
Universidad Nacional de Mar del Plata

Interfase dedicada compatible con Red Ethernet
María Isabel Schiavon, Daniel Crepaldo
Universidad Nacional de Rosario

Administrador de Paquetes para Capa de Protocolo USB 2.0
Diego E. Costa, Esteban M. Peláez, Carlos F. Sosa Páez, Héctor Vellón
Universidad Nacional de San Luis

A Soft Core for Pattern Recognition
Coral González-Concejero, Victoria Rodellar, Agustin Álvarez-Marquina, Elvira Martínez de Icaya, Pedro Gómez-Vilda
Universidad Politécnica de Madrid

Diseño e Implementación de una Unidad de Funciones Matemáticas
José Alberto Díaz García, Eugenio Salazar Brenes
Instituto Tecnológico de Costa Rica

Diseño de Aceleradores para el Alineamiento Global de Secuencias de ADN
Martin A. Lozano, Vladimir Trujillo-Olaya, Jaime Velasco-Medina
Universidad del Valle