There are several free training activities after the SPL 2007:
February 28, 2007 (at SPL Venue)
12:40-15:30 Synplicity Seminar: FPGA Synthesis with Synplify Pro® Software
15:30-17:00 ChipX Seminar: ASIC Design Methodology Basics and FPGA Conversions
March 1, 2007 (at SPL Venue)
09:00-11:00 11:30-12:30
March 12-14 and 19-21, 2007 (Universidad Nacional del Centro, Tandil, Argentina)
FPGAs Technology Course (in Spanish language)
Synplicity Seminar: FPGA Synthesis with Synplify Pro® Software
Date and Time: February 28, 2007, 12:40 to 15:30
Venue: Universidad CAECE, Mar del Plata
Language: English
Title: FPGA Synthesis with Synplify Pro® Software
Summary: This seminar introduces the new user to the Synplify Pro FPGA synthesis product. The course will familiarize the designer with the FPGA design flow utilizing features of the Synplify Pro product, enabling the designer to actively create designs using the Synplify Pro product. Topics Covered Include:
- Project Management
- Synthesis Concepts
- The Interactive Text Editor with Error Cross-probing
- HDL Coding for performance
- SCOPE® Graphical Constraints Entry
- The Finite State Machine Tools
- Mapping to FPGA Technologies
- Debugging with the HDL Analyst® Option
- Timing Analyzer
- Batch Mode
Speaker: Elías Todorovich, Universidad Autónoma de Madrid
ChipX Seminar: ASIC Design Methodology Basics and FPGA conversions
Date and Time: February 28, 2007, 15:30 to 17:00.
Venue: Universidad CAECE, Mar del Plata
Title: ASIC Design Methodology Basics and FPGA Conversions
Summary: The seminar covers things to be taken into consideration when converting an FPGA design to an ASIC. This seminar also covers good practices for Chip design in general. Topics included are:
- FPGA vs.. ASIC comparisons
- FPGA to ASIC conversion requirements
- Conversion Flow
- IP replacement
- Functional verification
- ASIC types and technologies
- Recommended and not recommended design practices
- Testability
- IO rules
- Design Flow
Speaker: Guillermo Casanova, CHIPX Corp. USA
Euroform Seminar: Embedded Systems on FPGAs
Date and Time: March 1, 2007, 09:00 to 11:00.
Venue: Universidad CAECE, Mar del Plata
Language: English
Title: Embedded Systems on FPGAs
Summary: TBD
Speaker: Gustavo Sutter, Universidad Autónoma de Madrid
Date and Time: March 1, 2007, 11:30 to 12:30.
Venue: Universidad CAECE, Olavarría Mar del Plata
Language: English
Title: Thermal Verification of FPGAs
Summary: This seminar summarizes a thermal monitoring strategy suitable for field programmable logic array (FPGA)-based systems. The main idea is that a fully digital temperature transducer can be dynamically inserted, operated, and eliminated from the circuit under test using reconfiguration. A ring-oscillator together with its auxiliary blocks (basically counting and control stages) is first placed in the design. After the actual temperature of the die is captured, the value is read back via the FPGA configuration port. Then, the sensor is eliminated from the chip in order to release programmable resources and avoid self-heating. The main advantage of the technique is that the sensor is completely stand-alone, no I/O pads are required, and no permanent use of any FPGA element is done. Additionally, the sensor is small enough to arrange an array of them along the chip. Thus, FPGAs became a new tool for researchers interested in the thermal aspects of integrated circuits.
Speaker: Eduardo Boemo, Universidad Autónoma de Madrid
FPGAs Technology Course
Dates: March 12-14 and 19-21, 2007.
Venue: Universidad Nacional del Centro, Tandil
Language: Spanish
Faculty: Gustavo Sutter and Elías Todorovich (Univ. Autónoma de Madrid)
Introduction: This course is oriented to professors, PhD candidates, researches and designers of digital circuits as well as directors of projects related to the design of electronic systems. The Laboratory work constitutes nearly the 50% of the total. The duration of the complete course is 45 hs.
The agenda has been separated in two parts. During March 12-14, the basic notions of VHDL language and basic utilization of Xilinx ISE tool are presented. Then, all the necessary knowledge to materialize a successful design with FPGAs is presented from March 19-21.
Module 1: VHDL Fundamentals
Introduction. Entity and architecture. Types. Signals, variables and constants. Operators. Processes and sensibility list. Sequential and concurrent sentences. Registers and synchronous circiuts. Implicit memory. State machines. High impedance Inference. Hierarchical design. Functional simulation with basic tesbenches. Complex tesbenches, procedures, functions and packages. Functional, post-synthesis and post-layout simulation.
Module 2: VHDL Lab
VHDL Design Flow. Simulation Tools. Useful tips editing VHDL, templates. Common errors in VHDL. Example circuits: Combinational circuits, registers, synchronous circuits, hierarchical design. Basic simulator commands and scripts. Basic and complex testbenches. Waveform and standard simulator outputs: analysis and tools.
Module 3: FPGA Fundamentals
The Evolution of Digital Technologies. Gate Arrays, Sea-of-Gates, Standard Cells. EDA Tools Design flow. Technology Mapping, Place-Route. Simulated Annealing. Architectures of FPGAs. Interconnections. Delay model. Skew and clock distribution. TSP Clocking. Simulation: Controllability and observability. Critical and false paths. High-speed design on FPGAs: Pipelining. Synchronization failures: Double and Clocking. Area -Time-Power figure.
Module 4: XILINX Technology Training Course
Xilinx XST. Design Entry Tools (HDL Editor, Core Generator, Schematic Editor, State Editor, PACE). Implementation Options. Analysis of Reports. Modelsim (Behavioral and Timing Simulation). Configuration Modes. User Constraint File (UCF). Optimization using Floorplanner and FPGA Editor tools. Advanced options of synthesis. RPM (relative location). Memory (distributed, double port, blockRAM, SRL), carry chains, embedded multipliers. DLL and DCM. Incremental design. Embedded Processors: An example with PicoBlaze.
The number of seats in the Tandil course is limited. If you are interested on it, you must fill a pre-registration in February 2007