IEEE


Keynote Speech

Dr. Reiner Hartenstein, IEEE Fellow, Reconfigurable Computing: boosting Software Education for the Multicore Era.



SPL2010 - Oral Session

Session W1 - Embedded Processors and IP Cores

Chair: Dr. Horacio C. Neto, INESC, Portugal

  • 11:00 - 11:20, "The Supersmall Soft Processor", "James Robinson","University of Toronto","Canada", "Sam Vafaee","University of Toronto","Canada", "Jonathan Scobbie","University of Toronto","Canada", "Michael Ritche","University of Toronto","Canada", "Jonathan Rose","University of Toronto","Canada"
  • 11:20 - 11:40, "LIBOR Market Model Simulation on an FPGA Parallel Machine", "Xiang Tian","The University of Edinburgh","United Kingdom", "Khaled Benkrid","The University of Edinburgh","United Kingdom"
  • 11:40 - 12:00, "Protection of Microprocessor-based Cores for FPL Devices", "Luis Parrilla","University of Granada","Spain", "Encarnación Castillo","University of Granada","Spain", "Antonio García","University of Granada","Spain", "Elías Todorovich","Universidad Autónoma de Madrid","Spain", "Daniel González","University of Granada","Spain"
  • 12:00 - 12:20, "FPGA-Based Smart Sensor Implementation With Precise Frequency to Digital Converter for Flow Measurement", "Edval J P Santos","Universidade Federal de Pernambuco","Brazil", "Leonardo B M Silva","Universidade Federal de Pernambuco","Brazil"
  • 12:20 - 12:40, "Acceleration of HMM-Based Speech Recognition System by Parallel FPGA Gaussian Calculation", "Richard Veitch","Queens University Belfast","United Kingdom", "Louis-Marie Aubert","Queens University Belfast","United Kingdom", "Roger Woods","Queens University Belfast","United Kingdom", "Scott Fischaber","Queens University Belfast","United Kingdom"

    Session W2 - Systems-on-Chip

    Chair: Dr. Gustavo Sutter, UAM, Spain

  • 14:40 - 15:00, "A Genetic Programming Based Approach for Efficiently Exploring Architectural Communication Design Space of MPSOCS", "Guilherme Esmeraldo","Informatics Center - Federal University of Pernambuco","Brazil", "Edna Barros","Informatics Center - Federal University of Pernambuco","Brazil"
  • 15:00 - 15:20, "An Environment for Energy Consumption Analysis of Cache Memories in SOC Platforms", "Filipe Cordeiro","UFPE","Brazil", "Abel Silva-Filho","UFPE","Brazil", "Cristiano Araújo","UFPE","Brazil", "Milena Gomes","UFPE","Brazil", "Edna Barros","UFPE","Brazil"
  • 15:20 - 15:40, "The Development of a Hardware Abstraction Layer Generator for System-on-Chip Functional Verification", "Tiago Lins","Federal University of Pernambuco - Informatics Center","Brazil", "Edna Barros","Federal University of Pernambuco - Informatics Center","Brazil", "Ralph Smeets","STMicroelectronics - Functional Verification Group","France"
  • 15:40 - 16:00, "A Placement Tool for a NOC-Based Dynamically Reconfigurable System", "Mario Raffo","University of Sao Paulo","Brazil", "Jonas Gomes Filho","University of Sao Paulo","Brazil", "Marius Strum","University of Sao Paulo","Brazil", "Wang Jiang Chau","University of Sao Paulo","Brazil"

    Session W3 - Computer Arithmetic

    Chair: Dr. Valentin O. Roda, USP-SC, Brazil

  • 16:20 - 16:40, "FPGA Based Floating-point Library for CORDIC Algorithms", "Daniel Muñoz","University of Brasília","Brazil", "Diego Sanchez","University of Brasília","Brazil", "Carlos LLanos","University of Brasília","Brazil", "Mauricio Ayala Rincón","University of Brasília","Brazil"
  • 16:40 - 17:00, "Montgomery Modular Multiplication on Reconfigurable Hardware: Fully Systolic Array vs Parallel Implementation", "Guilherme Perin","Universidade Federal de Santa Maria","Brazil", "Daniel Gomes Mesquita","Universidade Federal de Santa Maria","Brazil", "Fernando Luis Herrmann","Universidade Federal de Santa Maria","Brazil", "João Baptista dos Santos Martins","Universidade Federal de Santa Maria","Brazil"
  • 17:00 - 17:20, "Decimal division: algorithms and FPGA implementations", "Jean-Pierre Deschamps","University Rovira i Virgili","Spain", "Gustavo Sutter","Universidad Autonoma de Madrid","Spain"
  • 17:20 - 17:40, "Parallel Decimal Multipliers using Binary Multipliers", "Mário Véstias","INESC-ID/ISEL","Portugal", "Horácio Neto","INESC-ID/IST","Portugal"

    Invited Talk

    Michael (Mike) Mintz, Teal and Truss, Open Source Verification not Open Wallet



    Session T1 - Image Processing and Vision

    Chair: Dr. Eduardo Boemo, UAM, Spain

  • 11:00 - 11:20, "A High Performance Hardware Architecture for the H.264/AVC Half-Pixel Interpolation Unit", "Marcel Corrêa","Universidade Federal de Pelotas","Brazil", "Mateus Schoenknecht","Universidade Federal de Pelotas","Brazil", "Robson Dornelles","Universidade Federal de Pelotas","Brazil", "Luciano Agostini","Universidade Federal de Pelotas","Brazil"
  • 11:20 - 11:40, "FPGA-based Real Time Processing of the Plenoptic Wavefront Sensor for the European Solar Telescope (EST)", "Yolanda Martin","Instituto de Astrofísica de Canarias (IAC)","Spain", "Luis Fernando Rodríguez-Ramos","Instituto de Astrofísica de Canarias (IAC)","Spain", "Javier García-Jiménez","Instituto de Astrofísica de Canarias (IAC)","Spain", "Jose Javier Diaz-García","Instituto de Astrofísica de Canarias (IAC)","Spain", "Jose Maria Rodriguez-Ramos","Universidad de La Laguna (ULL)","Spain"
  • 11:40 - 12:00, "Architecture for Binary Mathematical Morphology Reconfigurable by Genetic Programming", "Emerson Carlos Pedrino","Federal University of Brazil from São Carlos","Brazil", "Valentin Obac Roda","São Paulo University from Brazil","Brazil"
  • 12:00 - 12:20, "An Optimized Label-Broadcast Parallel Algorithm for Connected Components Labeling", "Joao Teixeira","GRVM - UFPE","Brazil", "Bernardo Reis","GRVM - UFPE","Brazil", "Veronica Teichrieb","GRVM - UFPE","Brazil", "Judith Kelner","GRVM - UFPE","Brazil"

    Session F1 - FPGA Architectures for Specific Applications

    Chair: Dr. Edna Barros, UFPE, Brazil

  • 09:00 - 09:20, "A General-Purpose Dynammically Reconfigurable SVM", "Jonas Gomes Filho","University of Sao Paulo","Brazil", "Mario Raffo","University of Sao Paulo","Brazil", "Marius Strum","University of Sao Paulo","Brazil", "Jiang Chau Wang","University of Sao Paulo","Brazil"
  • 09:20 - 09:40, "FPGA Hierarchical Architecture for a Positron Emission Tomography Scanner", "Daniel Sebastián Estryk","Comisión Nacional de Energía Atómica","Argentina", "Claudio Abel Verrastro","Comisión Nacional de Energía Atómica","Argentina", "Sebastián Marinsek","Comisión Nacional de Energía Atómica","Argentina", "Martín Alberto Belzunce","Comisión Nacional de Energía Atómica", "Argentina","Esteban Venialgo","Comisión Nacional de Energía Atómica","Argentina"
  • 09:40 - 10:00, "An FPGA based architecture for Stateful inspection of multiple TCP connections", "Claudio Greco","University of Rome "Tor Vergata"","Italy", "Enrico Nobile","University of Rome "Tor Vergata"","Italy", "Salvatore Pontarelli","University of Rome "Tor Vergata"","Italy", "Simone Teofili","University of Rome "Tor Vergata"","Italy"

    Session F2 - Fault Tolerance, Test & Verification

    Chair: Dr. Edna Barros, UFPE, Brazil

  • 10:00 - 10:20, "Delay Modeling for Power Noise-Aware Design in Spartan-3A FPGAs", "Judit Fernandez Freijedo","University of Vigo","Spain", "Maria D. Valdes","University of Vigo","Spain", "Maria J. Moure","University of Vigo","Spain", "Lucia Costas Perez","University of Vigo", "Spain","Juan J. Rodriguez-Andina","University of Vigo","Spain"
  • 10:20 - 10:40, "Ring Oscillators Used as Thermal Sensors in FPGAs: Experiments in Low Voltage", "John Jairo León Franco","Universidad Autónoma de Madrid","Spain", "Sergio Lopez Buedo","Universidad Autónoma de Madrid","Spain", "Eduardo Boemo Scalvinoni","Universidad Autónoma de Madrid","Spain"

    SPL2010 - Poster Session

    Chair: Dr. Horacio C. Neto, INESC, Portugal

  • "Design and Implementation of Packet Switching Capabilities on 10GbE MAC Core", "Jorge M. Finochietto","Universidad Nacional de Córdoba - CONICET","Argentina", "Román A. Arenas","Universidad Nacional de Córdoba","Argentina", "Leonardo M. Rocha","Universidad Nacional de Córdoba","Argentina"
  • "Multiprotocol Transceiving, Formatting and Temperature Monitoring FPGA Based Unit", "Ricardo de Porras Bernácer","National Institute for Aerospace Technology (I.N.T.A.)","Spain"
  • "Motion Detection of Vehicles Based on FPGA", "Abel Silva-Filho","UFPE","Brazil", "Gilliano Menezes","UFPE","Brazil"
  • "A Reconfigurable General Framework for Pipelined Image Processing: A Color Mathematical Morphology Application", "Emerson Carlos Pedrino","Federal University of Brazil from São Carlos","Brazil", "Valentin Obac Roda","São Paulo University","Brazil", "José Hiroki Saito","Federal University of Brazil from São Carlos","Brazil"
  • "Full Duplex Implementation of Internet Protocol Version 4 in a FPGA Device", "Paulo César Comassetto de Aguirre","Federal University of Santa Maria","Brazil", "Lucas Teixeira","Federal University of Santa Maria","Brazil", "Crístian Muller","Federal University of Santa Maria","Brazil", "Fernando Luís Herrmann","Federal University of Santa Maria", "Brazil","Leandro Zafalon Pieper","Federal University of Santa Maria","Brazil"
  • "Using an FPGA Digital Clock Manager to Generate Sub-Nanosecond Phase Shifts for LIDAR Applications", "William Gaughan","Embry-Riddle Aeronautical University","United States", "Brian Butka","Embry-Riddle Aeronautical University","United States"
  • "Implementation of Split-Radix Fast Fourier Transform on FPGA", "Cynthia Watanabe","Pontificia Universidad Católica del Perú","Peru", "Carlos Silva","Pontificia Universidad Católica del Perú","Peru", "Joel Muñoz","University of São Paulo","Brazil"
  • "Efficiency Evaluation and Architecture Design of SSD Unities for the H.264/AVC Standard", "Gustavo Sanchez","Universidade Federal de Pelotas","Brazil", "Felipe Sampaio","Universidade Federal de Pelotas","Brazil", "Robson Dornelles","Universidade Federal de Pelotas","Brazil", "Luciano Agostini","Universidade Federal de Pelotas","Brazil"
  • "A Flexible Implementation of a Matrix Laurent Series-based Fast Fourier and Hartley 16-Point Transforms", "Raimundo C. de Oliveira","Amazon State University","Brazil", "Hélio M. de Oliveira","Federal University of Pernambuco","Brazil", "Ricardo C. de Souza","Federal University of Pernambuco","Brazil", "Edval J. P. Santos","Federal University of Pernambuco","Brazil"
  • "Implementation of a Sigmaboost-Based Ensemble of SVM in a Multiple Processor System on Chip", "Danniel Lopes","Universidade Federal Rural do Semi Arido - UFERSA","Brazil", "Naiyan Lima","Universidade Federal do Rio Grande do Norte - UFRN","Brazil", "Adriao Duarte","Universidade Federal do Rio Grande do Norte - UFRN","Brazil", "Jorge Melo","Universidade Federal do Rio Grande do Norte - UFRN","Brazil"
  • "Hardware Architectures for Fast Intermode Decision and for Residual Blocks in H.264/AVC Video Coding Standard", "Roger Porto","Federal University of Rio Grande do Sul","Brazil", "Luciano Agostini","Federal University of Pelotas","Brazil", "Sergio Bampi","Federal University of Rio Grande do Sul","Brazil"
  • "Rec-Bench: a Tool for Evaluating On-Line Task Scheduling algorithms in Reconfigurable Computers", "Mahmood Fazlali","Shahid Beheshti University","Iran, Islamic Republic Of", "Ali Zakerolhosseini","Shahid Beheshti University","Iran, Islamic Republic Of",
  • "Research and Partial Analysis of Overhead of a Partition Model for a Partially Reconfigurable Hardware in a Data-Driven Machine - ChipCflow", "Francisco de Souza Junior","Department of Computer Systems, University of São Paulo","Brazil", "Jorge Luiz e Silva","Department of Computer Systems, University of São Paulo","Brazil", "Lucas Sanches","Department of Computer Systems, University of São Paulo","Brazil", "Vitor Astolfi","Department of Computer Systems, University of São Paulo","Brazil"

    Designer Forum 2010 - Poster Session

    Chair: Dr. Cristiano C. Araujo, UFPE, Brazil

  • "Microcontrolador Compatible con AVR, Interfaz de Depuración y Bus WISHBONE", "Salvador Tropea","Instituto Nacional de Tecnología Industrial","Argentina", "David Caruso","Instituto Nacional de Tecnología Industrial","Argentina"
  • "Experiencia Académica sobre Incorporación de la Metodologia de Diseño Basada en HDL en una Carrera de Ingeniería Electrónica", "Roberto Martínez","Facultad de Cs. Exactas, Ingeniería y Agrimensura - Universidad Nacional de Rosario","Argentina", "Rosa Corti","Facultad de Cs. Exactas, Ingeniería y Agrimensura - Universidad Nacional de Rosario","Argentina", "Estela D'Agostino","Facultad de Cs. Exactas, Ingeniería y Agrimensura - Universidad Nacional de Rosario","Argentina", "Javier Belmonte","Facultad de Cs. Exactas, Ingeniería y Agrimensura - Universidad Nacional de Rosario","Argentina", "Enrique Giandoménico","Facultad de Cs. Exactas, Ingeniería y Agrimensura - Universidad Nacional de Rosario","Argentina"
  • "Audio sobre Ethernet: Implementación Utilizando FPGA", "Jose Mosquera","Universidad de Buenos Aires","Argentina", "Andres Stoliar","Universidad de Buenos Aires","Argentina", "Sol Pedre","Universidad de Buenos Aires","Argentina", "Maximiliano Sacco","Universidad de Buenos Aires","Argentina", "Patricia Borensztejn","Universidad de Buenos Aires","Argentina"
  • "Use of Self-Checking Logic to Minimize the Effects of Single Event Transients in Space Applications", "Juan Ortega-Ruiz","School of Computing engineering, Universidad Autonoma de Madrid","Spain", "Eduardo Boemo","School of Computing engineering, Universidad Autonoma de Madrid","Spain"
  • "Wireless Internet Configurable Network Module", "Maria Isabel Schiavon","Universidad Nacional de Rosario","Argentina", "Daniel Alberto Crepaldo","Universidad Nacional de Rosario","Argentina", "Raúl Lisandro Martín","Universidad Nacional de Rosario","Argentina"
  • "MIC - A New Compression Method of Instructions in Hardware for Embedded Systems", "Wanderson Roger Azevedo Dias","Universidade Federal do Amazonas - UFAM","Brazil", "Edward David Moreno","Universidade Federal de Sergipe - UFS","Brazil", "Raimundo da Silva Barreto","Universidade Federal do Amazonas - UFAM","Brazil"
  • "Embedded System that Simulates ECG Waveforms", "Thyago Maia Tavares de Farias","UNIVERSIDADE FEDERAL DA PARAÍBA - UFPB","Brazil", "José António Gomes de Lima","UNIVERSIDADE FEDERAL DA PARAÍBA - UFPB","Brazil"
  • "Fixed Point to Logarithmic Number System Convertions for Real Time Applications", "Fernando Ignacio Szklanny","Universidad Nacional de La Matanza","Argentina", "Carlos Eduardo Maidana","Universidad Nacional de La Matanza","Argentina", "Elio Augusto De María","Universidad Nacional de La Matanza","Argentina"
  • "Hardware Co-Processing Unit for Real Time Scheduling Analisys", "Jose Urriza","Universidad Nacional de la Patagonia San Juan Bosco","Argentina", "Ricardo Cayssials","Universidad Nacional del Sur","Argentina", "Edgardo Ferro","Universidad Nacional del Sur","Argentina"
  • "Implementação em Hardware do Método de Minkowsky para o Cálculo da Dimensão Fractal", "Maximiliam Luppe","USP","Brazil"
  • "An Entry-Level Platform For Teaching High-Performance Reconfigurable Computing", "Pablo Viana","Federal University of Alagoas","Brazil", "Dario Soares","Federal University of Alagoas","Brazil", "Lucas Torquato","Federal University of Alagoas","Brazil"
  • "Factorial Planning Appied to Energy Consumption Reduction in Architecture Exploration of Two-Level Memory Hierarchies", "Abel Silva-Filho","UFPE","Brazil", "Filipe Cordeiro","UFPE","Brazil"
  • "Derivación de claves PBKFD2 utilizando FPGA", "Sol Pedre","Universidad de Buenos Aires","Argentina", "Andrés Stoliar","Universidad de Buenos Aires","Argentina", "Patricia Borensztejn","Universidad de Buenos Aires","Argentina"
  • "Automatic Synthesis of Synchronous Controllers with Low Activity of the Clock", "Jozias Del Rios","Instituto Tecnológico de Aeronáutica","Brazil", "Leonardo Romano","Centro Universitário da FEI","Brazil", "Duarte Oliveira","Instituto Tecnológico de Aeronáutica","Brazil"
  • "Ajuste de Hierarquia de Memória para Redução de Consumo de Energia com Base em Otimização por Enxame de Partículas (PSO)", "Abel Silva-Filho","UFPE","Brazil", "Filipe Cordeiro","UFPE","Brazil", "Marcel Caraciolo","UFPE","Brazil", "Leopoldo Ferreira","UFPE","Brazil"
  • "IP-CORE de uma Memória Cache Reconfigurável", "Abel Silva-Filho","UFPE","Brazil", "Rodrigo Prado","UPE","Brazil", "Gabriel Gazineu","UFPE","Brazil", "Manoel Lima","UFPE","Brazil"
  • "A Note on Modeling Pulsed Sequential Circuits with VHDL", "Alberto Mesquita Jr.","Universidade Federal de Pernambuco","Brazil"
  • "Comparative Study Between the Implementations of Digital Waveforms Free of Third Harmonic on FPGA and Microcontroller", "Diogo Freitas","Universidade Federal de Pernambuco","Brazil", "Edval Santos","Universidade Federal de Pernambuco","Brazil"
  • "Towards an Energy-aware Design Method for Coarse-grained Reconfigurable Hybrid VLIW architectures", "Gustavo Cerezo","LSI-EPUSP","Brazil" "Wilhelmus A. Van Noije", "LSI-EPUSP","Brazil" "Nicolas J. S. Hervé", "LSITec", "Brazil"