Seminars
There are several free training activities before and after the SPL 2008:
March 25, 2008 (at INVAP SE, Bariloche)
08:30–13:00 Introduction to Digital Signal Processing (DSP) using FPGAs - Part I
15:00–20:00 Introduction to Digital Signal Processing (DSP) using FPGAs - Part II
March 28, 2008 (at SPL Venue)
14:30-17:00
March 31 to April 18, 2008 (Universidad Nacional del Centro, Tandil, Argentina)
Advanced Design Techniques for Digital Systems (in Spanish language)
March 31 to April 18, 2008 (Universidad Nacional de Mar del Plata, Argentina)
Functional Verification Primer (in Spanish language)
Introduction to Digital Signal Processing (DSP) using FPGAs
Date and Time: March 25, 2008, 08:30-13:00 and 14:00-17:00
Venue:
INVAP SE, Bariloche
211, Ruiz Moreno St. (on the corner of Ruiz Moreno and Mitre St.)
(about 400 m from the Conference Venue)Language: English
Title: FPGA Synthesis with Synplify Pro® Software
Preliminary Program:
Morning (08:30–13:00)
* Introduction to Digital Signal Processing (DSP)
What is DSP? How is it done? What platforms can be used? What tools are used.* Why do DSP with FPGAs?
Some comments on DSP algorithms and why to use FPGAs to implement them.* Issues related to DSP using FPGAs
Comments on clock and sampling frequencies, bit count, arithmetic operations.* FPGAs design flow for DSP applications
Design alternatives: HDLs, dedicated tools, etc.* Basic design example
Afternoon (15:00–20:00)
* Intro to Xilinx's System Generator
Introduction to Xilinx's SysGen tool and its integration to Matlab, Simulink and ISE* Use of Xilinx SysGen fro DSP
Sysgen use for simulation and synthesis..* More examples
* Other topics
Presentation of other tools and additional comments
Speaker: Guillermo Güichal, Universidad Tecnológica Nacional
The number of seats in this course is limited. If you are interested on it, please fill a pre-registration in before March 15, 2008.
Advanced Design Techniques for Digital Systems
Date and Time: March 28, 2008, 14:30-17:00
Venue: Conference Venue (Hotel Nevada)
Language: English
Title: Actel Seminar
Preliminary Program:
1) Overview of Actel's products (Commercial & Mil)
- Low Power Flash & the mixed signal Fusion technologies
2) IP / Micro offerings
3) Libero S/W suite
- demonstration of the Fusion toolset & power optimization tools
Speaker: Al Simon, Actel Corporation
Advanced Design Techniques for Digital Systems
Dates: March 31 to April 18, 2008
Venue: Universidad Nacional del Centro, Tandil
Language: Spanish
Faculty:
Elías Todorovich (Univ. Autónoma de Madrid)
Martin Vazquez (Universidad Nacional del Centro, Tandil)
Introduction: This course is oriented to professors, PhD candidates, researches and designers of digital circuits as well as directors of projects related to the design of electronic systems. The Laboratory work constitutes nearly the 50% of the total. The duration of the complete course is 45 hs.
The agenda has been separated in two parts. During the first part, the basic notions of VHDL language are reviewed. During the second part all the advanced VHDL 93 features are studied and the new VHDL 2008 are briefly presented. On the other hand Tcl/Tk is included in the course as the automation language for EDA tools.
Module 1: VHDL Fundamentals
Introduction. Entity and architecture. Types. Signals, variables and constants. Operators. Processes and sensibility list. Sequential and concurrent sentences. Registers and synchronous circuits. Implicit memory. State machines. High impedance Inference. Hierarchical design. Functional simulation with basic tesbenches.
Module 2: VHDL Lab
VHDL Design Flow. Simulation Tools. Useful tips editing VHDL, templates. Common errors in VHDL. Example circuits: Combinational circuits, registers, synchronous circuits, hierarchical design. Basic testbenches. Waveform and standard simulator outputs: analysis and tools.
Module 3: Advanced VHDL I
Generic constants. Complex instantiations. Configurations. Functional, post-synthesis and post-layout simulation. Time management inside the simulators.
Module 4: Advanced VHDL I Lab
A sequencial hierarchical design, the shift-and-add multiplier.
Module 5: Advanced VHDL II
Attributes. Alias. Complex tesbenches, procedures, functions and packages. Procedures and functions and synthesis. Records. Improving interfaces with records. Mixed Language Design.
Module 6: Advanced VHDL II Lab
Improving the design of a complex sequential system: a simple RISC microprocessor.
Module 7: VHDL 2008
Enhanced generics. Integrated PSL (Property Specification Language). Encryption of VHDL code sections. VHDL Procedural Interface (VHPI). News in the types and operations. New and changed statements. Improved design flexibility. Future VHDL: OO, randomization, functional coverage.
Module 8: Tcl/Tk for EDA Tools
Introduction. The Tk toolkit. Syntax and substitution rules. Commands. Extending Tcl. Developing GUIs with Tk. Tcl/Tk for EDA tools: Mentor Graphics, Altera, Xilinx, Synplicity. App. Examples. Case study: Tcl for Xilinx ISE.
Module 9: Tcl/Tk for EDA Tools Lab
Automating simulations in Mentor Graphics Modelsim. Automating synthesis and FPGA implementation in Xilinx ISE.
If you are interested on it, please contact Martin Vazquez (mvazquez@exa.unicen.edu.ar).
Functional Verification Primer
Dates: March 31 to April 18, 2008
Venue: Universidad Nacional de Mar del Plata
Language: Spanish
Faculty:
Elías Todorovich (Univ. Autónoma de Madrid)
Carlos Gayoso (Universidad Nacional de Mar del Plata)
Claudio González (Universidad Nacional de Mar del Plata)
The course introduces modern views driven the EDA industry for building Functional Verification (FV) environments. Participants will exercise a FV flow under Questa by hands-on real design examples of digital circuits specified in VHDL.
Contents:
1) VHDL Fundamentals
Introduction. Entity and architecture. Types. Signals, variables and constants. Operators. Processes and sensibility list. Sequential and concurrent sentences. Registers and synchronous circuits. Implicit memory. State machines. High impedance Inference. Hierarchical design. Functional simulation with basic tesbenches.
Practical and exercises: VHDL Design Flow. Simulation Tools. Useful tips editing VHDL, templates. Common errors in VHDL. Example circuits: Combinational circuits, registers, synchronous circuits, hierarchical design. Basic testbenches. Waveform and standard simulator outputs: analysis and tools.
2) Traditional Verification
Verification of IP cores. Concepts and terminology. Verification flow. Verification plan. Inspection. Adversarial testing. Testbench design. Design of verification components. Code coverage. Timing verification.
Practical and Exercises: Verification by code and design inspection. Code Coverage in Questa (Tutorial Ch 12)
3) Assertion based verification
Assertions structure. Writing assertions. Property Specification Language (PSL). Use of PSL in Questa.
Practical and exercises: Mounting of previous VHDL designs to: Verification with Questa: Tutorial Verification with PSL (Ch 13). Writing assertions to verify basic operations of the design. Binding PSL to VHDL components using Questa.
4) VHDL 2008
Enhanced generics. Integrated PSL (Property Specification Language). Encryption of VHDL code sections. VHDL Procedural Interface (VHPI). News in the types and operations. New and changed statements. Improved design flexibility. Future VHDL: OO, randomization, functional coverage.
5) Advanced ABV
Functional Coverage Methodology. Assertion Patterns. Verification Libraries. Open Verification Library (OVL).
Practical and exercises: Adding coverage to previous design example using Questa. Applying assertions patterns to existing designs
Last Update 19.03.2008