FPGAs Course (Altera and Xilinx technologies)
Mar del Plata - March 2-3 and 6-7, 2006
This course is oriented to professors, PhD candidates, researches and designers of digital circuits as well as directors of projects related to the design of electronic systems. The Laboratory work constitutes nearly the 60% of the total. The duration of the complete course is 40 hs.
For flexibility, the agenda has been separated in two parts. During Thursday and Friday, the basic notions of VHDL language and basic utilization of Xilinx ISE tool are presented. Then, all the necessary knowledge to materialize a successful design with FPGAs is presented from Monday to Wednesday.
2006 Course reservation is closed.
Timetable of the teaching modules is available. Each registered person will receive a e-mail of acceptance by February 6. Considering than the number of applications is much bigger than the lab capacity some persons have been accepted only for the theoretical lectures.
The keywords for each module are:
Module 1: VHDL Fundamentals
Coordinador: Elías Todorovich, Universidad Autónoma de Madrid , Spain
Introduction. Entity and architecture. Types. Signals, variables and constants. Operators. Processes and sensibility list. Sequential and concurrent sentences. Registers and synchronous circiuts. Implicit memory. State machines. High impedance Inference. Hierarchical design. Functional simulation with basic tesbenches. Complex tesbenches, procedures, functions and packages. Functional, post-synthesis and post-layout simulation.
Module 2: VHDL Lab
Coordinador: Elías Todorovich, Universidad Autónoma de Madrid , Spain
VHDL Design Flow. Simulation Tools. Useful tips editing VHDL, templates. Common errors in VHDL. Example circuits: Combinational circuits, registers, synchronous circuits, hierarchical design. Basic simulator commands and scripts. Basic and complex testbenches. Waveform and standard simulator outputs: analysis and tools.
Module 3: FPGA Fundamentals
Coordinador: Eduardo Boemo, Universidad Autónoma de Madrid , Spain
The Evolution of Digital Technologies. Gate Arrays, Sea-of-Gates, Standard Cells. EDA Tools Design flow. Technology Mapping, Place-Route. Simulated Annealing. Architectures of FPGAs. Interconnections. Delay model. Skew and clock distribution. TSP Clocking. Simulation: Controllability and observability. Critical and false paths. High-speed design on FPGAs: Pipelining. Synchronization failures: Double and Clocking. Area -Time-Power figure.
Module 4: XILINX Technology Training Course
Coordinador: Gustavo Sutter, Universidad Autónoma de Madrid , Spain
Xilinx XST. Design Entry Tools (HDL Editor, Core Generator, Schematic Editor, State Editor, PACE). Implementation Options. Analysis of Reports. Modelsim (Behavioral and Timing Simulation). Configuration Modes. User Constraint File (UCF). Optimization using Floorplanner and FPGA Editor tools. Advanced options of synthesis. RPM (relative location). Memory (distributed, double port, blockRAM, SRL), carry chains, embedded multipliers. DLL and DCM. Incremental design. Embedded Processors: An example with PicoBlaze.
Module 5: ALTERA Technology Training Course
Coordinador: Andrés García García, Tecnológico de Monterrey, México.
VHDL Review. Evolution of PLDs. Altera CPLDs and FPGAs. Details of Altera FPGA Architectures. First steps with Quartus II. Workspace. Packaging. IO capabilities. Clock in Altera devices. Embedded resourses. Design Tools: Quartus II, design entry tools, synthesis and simulation. VHDL for synthesis. Chip programming alternatives. Soft Processors. Low-Power Design in Altera. Educational and development boards. Altera University Program.
Faculty:
Dr. Eduardo Boemo . (Univ. Autónoma de Madrid)
Dr. Andrés David García García (Inst. Tecn. de Monterrey)
Dr. Sergio López Buedo (Univ. Autónoma de Madrid)
Dr. Gustavo Sutter (Univ. Autónoma de Madrid)
Ing. Elías Todorovich (Univ. Autónoma de Madrid)
Ing. Martín Vázquez (Univ. Nac. del Centro, Tandil)
Ing. Salvador Trapea (INTI, Argentina)
Ing. Guillermo Guichal (UTN Bahía Blanca)